Preliminary considerations on the strip readout chip for SVT Parameter space Tracking efficiency Peaking time (Buffer lengths) M. Villa – Bologna 15/04/2011

Parameter space SVT as designed: L1-L5 + L0(striplets) Gangling/Occupancy/Simulations Several unknowns: exact background rate; hit multiplicities Trigger frequency: 150 kHz (1.5 S.F) jitter: 100 ns (the goal is to go down to 30 ns) latency: 10 us (1.7 SF; LVL1 design is 6 us) DAQ window: 100ns+2 Time stamps or 300 ns Time stamping: 30 MHz (5-40 MHz) Chip readout clock: 50 MHz (56-112 MHz ?)

Tracking efficiency

What value for the minimum strip efficiency? Main requirement: 98% SVT-only tracking efficiency (L1-L5) Tracking conditions: At least spacepoints on 4 layers (out of 5) Spacepoints in x and y (u and v) 2 hit strip/cluster (1 hit strip/cluster) Doubtfull if inefficiencies on adiacent strips can be considered uncorrelated! Mean hit multiplicity/track usually high (>=2)

Results from simple calculation: εT=98% SVT-only tracking efficiency when: εL=95.3 % efficiency on each layer (and asking at least 4 layers with spacepoints) εSS=97.6 % single side efficiency (single sides are considered uncorrelated) Individual strip efficiency : 97.6 % for 1 hit/cluster 97.6 % for n correlated hit/cluster (pessimistic) 84.7 % for 2 hit/cluster uncorrelated (over-optimistic) 91.2 % guess estimation for 50% sharing or correlation (reasonable/optimistic(?))

A little bit of systematics Tracking efficiency 95.0 % 97.0 % 98.0 % 99.0 % 99.5 % Layer eff (5 layer tracking [l.tr.]) 99.4 % 99.6 % 99.8 % 99.9% Layer eff (>=4 l. tr.) 92.4 % 94.2 % 95.3 % 96.7 % 97.7 % Single side eff (>=4 l.tr.) 96.1 % 97.1 % 97.6 % 98.4 % 98.8 % Strip efficiency 1 hit/cluster or N correlated hits 2 uncorrelated hits/cluster 80.3 % 82.8 % 84.6 % 87.2 % 89.3 % Reasonable (?) mean. 88.2 % 89.9 % 91.1 % 92.8 % 94.1 %

Peaking time

Analog efficiency estimations Assumptions: Strip dead time equal to 2.4 peaking time Strip rates as given by Roberto C. (?): L0: 2060 kHz/strip L1: 268 kHz/strip L2: 179 kHz/strip L3: 52.5 kHz/strip L4: 21.9 kHz/strip L5: 18.7 kHz/strip

Efficiency vs peaking time No safety factor Safety factor of 5 L5 L5 L4 L4 L3 L2 L0 L0 L1 L1 L2 L3 97.6% eff Tp(L1)=190 ns 97.6% eff Tp(L1)=38 ns

A comment on safety factors Stainless steel safety factors used in industries: 3 or above for buildings No problem on additional weight 1.65 for large antennas Additional weight starts to be a problem 1.15 (!!) for plane wings Useless weights keep a plane on the ground Lesson here: complex systems (like SVT) might fail if too large safety factors are used!! Conflicting requirements: Capability to deal efficiently with high rates low Tp Signal separation, dE/dx performances  high Tp By the way: this is not the only place where large safety factors can be problematic

Max Peaking times (ns) at fixed strip efficiency Target strip efficiency 97.6% 95% 91% SF=5 SF=1 L0 5 25 10 52 19 95 L1 38 189 80 399 147 733 L2 57 283 119 597 220 1098 L3 193 964 307 Max 748 L4 462 976 1794 L5 541 1142 Max = what allowed by the 6 us max trigger latency = approx 2 us.

Peaking times for next calculations L0: 25 ns L1-L2-L3: 100 ns L4-L5: 1000 ns

Readout chip for strips ~hit_rate * trig_latency Sparsifier strip #127 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 strip #0 FE ADC Or ToT Ctrl logic Buf #k ... Buf #1 BUF #1 Triggered hits only readout/slow control First buffering per strip then transfer triggered time stamps Re-use of digital readout logic developed for pixels

First guess on number of buffers required for L0 striplets/L1 strip Assume L0 @ 225 MHz/cm2, L1@5 MHz/cm2 L0 = 2 MHz/strip, L1=270 KHz/strip Just calculations; Mini-MC simulation needed F. Morsani

Layers L2-L3; L4-L5 L2-L3: 100 ns peaking time -> 240 ns dead time; Max 42 hits in 10 us; Efficiency always >= eff on L1 L4-L5: 1 us peaking time -> 2.4 us dead time; Max 5 hits in 10 us; Efficiency 100 % already with 5 buffers

Design choice ahead Coupling of fixed latency part with triggered part: Synchronous: triggered his are transfered in one clock cycle on the second part Fits better with the buffer logic Pixel readout not suitable Asynchronous: triggered hits stay in the buffers till reading (as hit pixels in matrix) Fits perfectly with the pixel readout architecture Hit transferring can be fast: 2-3 clock cycles (but not 1 clock!).

Summary Relation between strip efficiency and track efficiency Peaking time ranges Choices of safety factors Too large in the past? Most of the inefficiency can be kept in the analog part of the chip Reuse of the pixel chip readout architecture possible, but need planning.