Accelerating Genome Sequencing 100X with FPGAs

Slides:



Advertisements
Similar presentations
Presented by Field-Programmable Gate Array Research Speeds HPC up to 100X Olaf O. Storaasli Future Technologies Group Computer Science and Mathematics.
Advertisements

EEL6686 Guest Lecture February 25, 2014 A Framework to Analyze Processor Architectures for Next-Generation On-Board Space Computing Tyler M. Lovelly Ph.D.
Timothy Blattner and Shujia Zhou May 18, This project is sponsored by Lockheed Martin We would like to thank Joseph Swartz, Sara Hritz, Michael.
Boosting XML filtering through a scalable FPGA-based architecture A. Mitra, M. Vieira, P. Bakalov, V. Tsotras, W. Najjar.
Implementation methodology for Emerging Reconfigurable Systems With minimum optimization an appreciable speedup of 3x is achievable for this program with.
DUKE CSNUFFT on Multicores HPEC-2008 Sept. 25, 2008NUFFTs on Multicores 1 Parallelization of NUFFT with Radial Data on Multicore Processors Nikos Pitsianis.
Multithreaded FPGA Acceleration of DNA Sequence Mapping Edward Fernandez, Walid Najjar, Stefano Lonardi, Jason Villarreal UC Riverside, Department of Computer.
Silicon Graphics, Inc. Poster Presented by: SGI Proprietary Technologies for Breakthrough Research Rosario Caltabiano North East Higher Education & Research.
Some Thoughts on Technology and Strategies for Petaflops.
Reconfigurable Application Specific Computers RASCs Advanced Architectures with Multiple Processors and Field Programmable Gate Arrays FPGAs Computational.
Hypercomputing With the CORDIC Algorithm
Seven Minute Madness: Reconfigurable Computing Dr. Jason D. Bakos.
Heterogeneous Computing Dr. Jason D. Bakos. Heterogeneous Computing 2 “Traditional” Parallel/Multi-Processing Large-scale parallel platforms: –Individual.
Introduction to Reconfigurable Computing Greg Stitt ECE Department University of Florida.
Networking Virtualization Using FPGAs Russell Tessier, Deepak Unnikrishnan, Dong Yin, and Lixin Gao Reconfigurable Computing Group Department of Electrical.
12005 MAPLDBOF-H-2 BOF-H-2 Programming Tools for General Purpose High Performance Reconfigurable Computers BOF hosted by Douglas Fouts & Alan Hunsberger.
© Fujitsu Laboratories of Europe 2009 HPC and Chaste: Towards Real-Time Simulation 24 March
Time Integration Utilities on an FPGA Cris A. Kania with Olaf O. Storaasli, Ph. D. NASA Langley.
OCCBIO 2007 Tutorial on FPGA-Acceleration Processors.
Accelerating Progress in Bioinformatics: Education, Technology, Infrastructure, and Application OCCBIO 2007 Panel Discussion.
Engineering Applications on
Future Requirements for NSF ATM Computing Jim Kinter, co-chair Presentation to CCSM Advisory Board 9 January 2008.
COMPUTER SCIENCE &ENGINEERING Compiled code acceleration on FPGAs W. Najjar, B.Buyukkurt, Z.Guo, J. Villareal, J. Cortes, A. Mitra Computer Science & Engineering.
Parallel Computing Using FPGA ( Field Programmable Gate Arrays ) 15 th May, 2009 Studies in Parallel & Distributed Systems – Sohaib Ahmed.
Uncovering the Multicore Processor Bottlenecks Server Design Summit Shay Gal-On Director of Technology, EEMBC.
Reckless Speeding The investigation of the programming capabilities of the HAL hypercomputer Reese Dandawate Governor’s School NASA mentorship July 25,
Taking the Complexity out of Cluster Computing Vendor Update HPC User Forum Arend Dittmer Director Product Management HPC April,
Slide 1 Starbridge Viva™ Starbridge Solutions to Supercomputing Problems Reconfigurable Systems Summer Institute Esmail Chitalwala Starbridge Customer.
Reminder Lab 0 Xilinx ISE tutorial Research Send me an if interested Looking for those interested in RC with skills in compilers/languages/synthesis,
Efficient Data Accesses for Parallel Sequence Searches Heshan Lin (NCSU) Xiaosong Ma (NCSU & ORNL) Praveen Chandramohan (ORNL) Al Geist (ORNL) Nagiza Samatova.
VTU – IISc Workshop Compiler, Architecture and HPC Research in Heterogeneous Multi-Core Era R. Govindarajan CSA & SERC, IISc
Computing Faster Without CPUs GOAL: Evaluate FPGA*-based Hypercomputer Potential for NASA Scientific Computations * Field-Programmable Gate Array (e.g.
MAPLD Reconfigurable Computing Birds-of-a-Feather Programming Tools Jeffrey S. Vetter M. C. Smith, P. C. Roth O. O. Storaasli, S. R. Alam
VLSI Algorithmic Design Automation Lab. 1 Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.
HPC User Forum Back End Compiler Panel SiCortex Perspective Kevin Harris Compiler Manager April 2009.
Storaasli 5/9/03 Analytical and Computational Methods Computing Faster without CPUs Scientific Applications on FPGA-based* Reconfigurable Hypercomputers.
Software Working Group Chairman’s Note: This document was prepared by the “software and applications” working group and was received by the entire workshop.
One step ahead. The Challenges of Architectures that Grow to Petascale and can be Sustained Economically Steve Reinhardt Principal Engineer, SGI spr at.
1 - CPRE 583 (Reconfigurable Computing): Reconfigurable Computing Systems Iowa State University (Ames) CPRE 583 Reconfigurable Computing Lecture 8: Wed.
Biocomputation: Comparative Genomics Tanya Talkar Lolly Kruse Colleen O’Rourke.
Accelerating Bioinformatics Algorithms with Reconfigurable Computing Presentation to MAPLD Conference September 2004.
IMP: Indirect Memory Prefetcher
Biosequence Similarity Search on the Mercury System Praveen Krishnamurthy, Jeremy Buhler, Roger Chamberlain, Mark Franklin, Kwame Gyang, and Joseph Lancaster.
Cray XD1 Reconfigurable Computing for Application Acceleration.
© 2009 Altera Corporation Floating Point Synthesis From Model-Based Design M. Langhammer, M. Jervis, G. Griffiths, M. Santoro.
Reconfigurable Supercomputing (2) Key Issues in HPC  Leveling off of performance Traditional Scalar/Vector – long product cycles, too few vendors.
TEMPLATE DESIGN © H. Che 2, E. D’Azevedo 1, M. Sekachev 3, K. Wong 3 1 Oak Ridge National Laboratory, 2 Chinese University.
Presented by Reconfigurable HPC Research at ORNL using Field-Programmable Gate Arrays (FPGAs) Olaf O. Storaasli Future Technologies Group Computer Science.
CORDIC Based 64-Point Radix-2 FFT Processor
Auburn University COMP7330/7336 Advanced Parallel and Distributed Computing Exploratory Decomposition Dr. Xiao Qin Auburn.
EEE4084F Digital Systems NOT IN 2017 EXAM Lecture 25
High Performance Computing on an IBM Cell Processor --- Bioinformatics
BLAST Anders Gorm Pedersen & Rasmus Wernersson.
FPGAs in AWS and First Use Cases, Kees Vissers
EEL4720/5721 Reconfigurable Computing
Introduction to Reconfigurable Computing
Performance and Code Tuning
Parallel Computers Today
EEE4084F Digital Systems NOT IN 2018 EXAM Lecture 24X
Instructor: Dr. Phillip Jones
Adnan Salman1 , Sergei Turovets1, Allen Malony1, and Vasily Volkov
Alternative Processor Panel Results 2008
Instructor: Dr. Phillip Jones
Accelerating Bioinformatics Algorithms with Reconfigurable Computing
Back End Compiler Panel
Greg Stitt ECE Department University of Florida
Star Bridge Systems, Inc.
_____’s November Student-Led Conference
Computing as Fast as an Engineer can Think
Reconfigurable Computing (EN2911X, Fall07)
Presentation transcript:

Accelerating Genome Sequencing 100X with FPGAs Good Morning! I’m O.S. formerly of NASA LaRC. I joined the FTG last fall to “Explore RC……. I’m happy to be here & share progress on this 2-yr LDRD which officially began in February Accelerating Genome Sequencing 100X with FPGAs Olaf Storaasli - HPEC07, MIT Lincoln Labs • Relevance • Accomplishments • Summary 1

Increasing FPGA Relevance to HPC “After exhaustive analysis, Cray concluded that, although multi-core commodity processors will deliver some improvement, exploiting parallelism through a variety of processor technologies using scalar, vector, multithreading & hardware accelerators (e.g., FPGAs or ClearSpeed co-processors) creates the greatest opportunity for application acceleration” HPCWire 24 March ‘06 HPC Future, Steve Scott, Cray CTO: DRC FPGA Coprocessors in HPCS & Cray XT Virtex4 FPGA blades to: “Accelerate mission-critical applications by over 100x” FPGAs (Altera) Many recognize what RC (FPGAs) bring to HPC, including Cray. Steve Scott, Cray, CTO expressed Cray’s view of future HPC to HPCWire: Then in May, Cray announced their Adaptive Computing Strategy and selected DRC FPGA Coprocessors for HPCS & future Supercomouters. Earlier, Jan Silverman asked my views on ACS and asked if we’d like to test DRCs at ORNL. Linux Networx & IBM have recently shown their hand joining Cray, SGI, SRC in reconfigurable computing (next slide). The potential to exceed 1 petaflop quickly (at reduced power) is great indeed. Opteron Socket Potential: Petaflops/Exaflops at reduced power

FPGA Coding: Graphical vs Text

Viva Algorithms Developed* • n! => Probability: Combinations/Permutations • Cordic => Transcendentals: sin, log, exp, cosh… • ∂y/∂x & ∫ f(x)dx => Runge-Kutta: CFD, Newmark Beta: CSM • Matrix Equation Solvers: [A]{x} = {b}, Gauss & Jacobi • Nonlinear Analysis: reduces NL time • Matrix Algebra: {V}, [M], {V}T{V}, [M]x[M],GCD,… . • Dynamic Analysis: [M]{ü} + [C]{u} + [K]{u} + NL = {P(t)} • Structural Design/Optimization • Unsolved App: Traveling Salesman I find Viva intuitive & logical and straight-forward developing algorithms (below) Brought to ORNL from NASA along with GPS (Nike3D)

Climate/Weather Code: CHiMPS FPGA Port MD CHiMPS port took 20 min + 20 min to optimize

10X* FPGA Speedup for Matrix Equation Solver 36X for LU Decomposition Benefits: High performance of LP arithmetic High precision accuracy Speedup increases with matrix size First mixed-precision LU & solver for FPGAs *vs 2.2 GHz Opteron

Smith-Waterman Benchmark • FASTA genome matching application http://fasta.bioch.virginia.edu • Uses search34 code & Cray SW core • NCBI Human Genome Data: 4GB compressed Case 1: Micro-RNA, Case 2: DNA I hope you agree that this research is: “Increasingly … Thank you for your attention.

100X* Cray XD1 Virtex-4 Speedup* Genome Sequence FPGA Speedup 8 hrs => 5 min *vs 2.2 GHz Opteron

FPGA Speedup grows with Query Size

Next: Expected Results *Reconfigurable Application Specific Computing • DRC LX200 (89k/68k = 1.3) => 130X => Cray XT4 • 144 Cray XD1 FPGAs => 144X50+ => 7,200X • New CHiMPS (climate, MD, solver apps) => paper • New SGI RASC* (Virtex4): BLAST 60X, FASTA,… RASC *Reconfigurable Application Specific Computing

• Next: Summary Increased FPGA HPC relevance: speed, power Growth: team, H/W, tools & Apps (+$0.0) - FPGAs: Cray, SGI, SRC, Nallatech, Digilent + Bee2, DRC - Tools: Mitrion-C, Carte, Viva, CHiMPS - Apps: STSWM, FASTA, MD, BLAST & Matrix Eqn. Solver Results: FASTA Speedups: 50X (V2), 100X (V4) Solver 10X (V2), BLAST 60X (V4) + MD 10X, STSWM NDA • Next: 144 FPGAs, DRC LX200 => XT4 => ORNL Path CHiMPS & SGI/RASC Application performance Publish results I hope you agree that this research is: “Increasingly … Thank you for your attention.