IAY 0600 Digital Systems Design Digitaalsüsteemide disain Course Overview Alexander Sudnitson Tallinn University of Technology

Administrative Aleksander Sudnitsõn (Alexander Sudnitson) Department of Computer Engineering (Arvutitehnika instituut) Associate Professor (dotsent) ICT-503 aleksander.sudnitson@ttu.ee Tel. +372 5092356 www.pld.ttu.ee/~alsu

Course resources www.pld.ttu.ee/~alsu IAY0600 Digital Systems Design (LECTURES) Digitaalsüsteemide disain IAY0600l Digital Systems Design (WORKSHOPS) Digitaalsüsteemide disain (LABS)

Lectures http://ati.ttu.ee/~alsu/IAY0600.html Lecture: Wednesday 14.00 - 15.30 http://ati.ttu.ee/~alsu/IAY0600.html

Labs Wednesday 16.00 - 17.30 B. Wednesday 17.45 - 19.15 Assistant: research scientist, Dimitri Mihhajlov, PhD Technical Assistant: early stage researcher Artjom Rjabov, PhD student: Aleksei Obuhhov

Labs http://ati.ttu.ee/~alsu/IAY0600l.html IAY0600l

Grading “LEARN BY DOING” To stimulate the student’s activity a project-based evaluation approach is adopted. Grading consists of control of knowledge in examinations and of the demonstration of the projects and the quality of a written reports (40 points in final grade for doing compulsary labs, up to 70 points in final grade for doing optional labs). Exam gives max 30 points. “LEARN BY DOING” Learning By Example Using VHDL (with FPGA Evaluation Boards)

Passing a Lab Every completed experiment (project) must be presented to Assistant (D. Mihhailov), who will evaluate student’s results and effort Each lab is passed in three steps: Step 1: Visual demonstration Step 2: Submission of the report Step 3: Defence/discussion of the report Labs can be done either individually, or in teams of two. Note, that in case of teamwork Step 2 and Step 3 MUST be done by each team member separately.

Compulsory Labs Labs labelled “compulsory” form the basic core of the course. In order to pass the course these labs MUST be completed within the deadline. Passing all compulsory labs yields the minimum positive final grade and allows possibility to attend the exam.

Labs schedule - Tutorials Week 1: Tutorial (Vivado) - Compulsory labs Week 2: Lab 2 (Comparator) Week 4: Lab 3 (Adder) Week 6: Lab 4 (Parameterizable Adder) Week 8: Lab 5 (Serial Adder) - Optional labs Week 10: Lab 6 (Finite-State Machine) Week 11: Lab 7 (Greatest Common Divisor) Week 13: Lab 8 (LFSR) Week 14: Lab 9 (Creeping Line)

Optional Labs Labs labelled “optional” are more advanced labs that are not required to be completed in order to pass the course. However, each successfully passed optional lab increases the final grade (up to the maximum for doing all optional labs).

Labs Xilinx FPGA Tools The laboratory assignments are done using the Xilinx ISE Software and Vivado. simulation synthesis implementation Digilent Nexys4 and ZedBoard FPGA Boards

Course goals to elaborate knowledge of the design process from design description in VHDL through functional simulation, synthesis, timing simulation, and PLD (FPGA) programming; to gain experience in designing and verifying digital systems using synthesis and simulation tools; to provide students the theory and practice of rapid prototyping of digital systems in a laboratory environment;

Outcomes to proceed from a digital system description in VHDL to its implementation in a PLD (FPGA) using of a number of computer-aided design software tools; to understand how to interpret design tool outputs in evaluating alternative system designs for a specific set of requirements, and how to use the knowledge gained to improve the design.

Why is this course worth taking? VHDL for synthesis: one of the most sought-after skills knowledge of state-of-the-art tools used in the industry knowledge of the modern FPGA & ASIC technologies unique knowledge and practical skills that make you competitive on the job market

Main topics The course is based on the development of a real-world projects and case studies Synthesizable VHDL Digital systems design methodology using VHDL and PLD (FPGA) FPGAs as means for building reconfigurable systems Rapid prototyping of digital systems.

Slides http://ati.ttu.ee/~alsu/IAY0600.html Lecture slides (to be published before each lecture). Auxiliary material: Digital Systems Modelling and Synthesis http://www.ati.ttu.ee/IAY0340/

Textbooks Short K. L. VHDL for Engineers, Pearson Education, Inc., 2009, 2013. Chu P.P. FPGA Prototyping Using VHDL Examples: Xilinx Spartan-3 Version, Jonh, Willey & Sons, 2008. Pedroni V. A. Circuit Design and Simulation with VHDL, Massachusetts Institute of Technology, 2010. Skljarov V., Skliarova I., Sudnitson A. Design of FPGA- based Circuits using Hierarchical Finite State Machines. TUT Press, Tallinn, 2012, 240 p. Sarah L. Harris & David M. Harris, "Digital Design and Computer Architecture“, Elsevier, 2016.