How to debug PMP systems A guideline for Application Engineers Vincenzo Pizzolante November 2013

Agenda Section I – The path of the analysis Section II – The technical aspects Section III – When guilty is the layout TI Information – Selective Disclosure

Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information – Selective Disclosure

Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information – Selective Disclosure

Trace Inductance Typical 10mils trace

Case Study: Ideal World Is Is current source Vc Vc

Case Study: Non Ideal World stray inductance (PCB traces) Is Is current source Vc Vc

Case Study: Non Ideal World High di/dt Is Is current source Vc High EMI Vcg Vcg Vc High di/dt causes noise accross stray inductance!

Impact of High di/dt First, identify high di/dt paths VIN Vout All elements, including PCB traces, have parasitic L, R, C High di/dt thru parasitic L produces voltage spikes Must avoid injecting these currents into the ground plane First, identify high di/dt paths

How to Deal with the Noise Generators VIN Vout Note the re-route of the diode-return path Forces pulse currents directly back to input cap Keeps high di/dt currents out of ground Diode anode may actually be a bit noisier, but who cares? Can apply the same rationale to all topologies

Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information – Selective Disclosure

Locating the high di/dt paths Buck Boost Sepic

Buck: High di/dt Paths Draw the switch-ON current path in one color Then draw the switch-OFF path in another Any part of the circuit that has only a single color, or both with current arrows in opposite direction, is a high di/dt path Works for all topologies! High di/dt

Buck: High di/dt Paths Identified #1 Most important paths! Keep this GND path separated from the GND plane!

Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information – Selective Disclosure

Example with Lab Results This is the schematic of an actual LM3100 demo board

VO (AC) With Improper Layout 250MHz Bandwidth, 100mV/div 20MHz Bandwidth, 100mV/div

Improper Layout Artwork LM3100 Rev. B - Problem layout: Top Silk Bottom copper Top copper

Recall Buck di/dt Paths #1 Most important paths! Keep this GND path separated from the GND plane!

Improper Layout Artwork - The Critical Paths - Red = Bottom Blue = Top

Improved Layout Artwork LM3100 Rev. C - Proper layout: Top Silk Bottom copper Top copper

Improper Layout Artwork - The Critical Paths - Red = Bottom Blue = Top

VO (AC) With Improper Layout (Rev. B) 250MHz Bandwidth, 100mV/div 20MHz Bandwidth, 100mV/div

VO (AC) Improved Layout (Rev. C) 250MHz Bandwidth, 20mV/div 20MHz Bandwidth, 20mV/div

Improved Layout Effects 20MHz Bandwidth, 100mV/div (Rev. B) 20MHz Bandwidth, 20mV/div (Rev. C)

Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information – Selective Disclosure

4-Layers PCB Desired Undesired Layer 1 – Power components Layer 2 – Small signal Layer 3 – GND plane Layer 4 – Small signal / controller Switching currents from power components to GND plane cause capacitive cross-talk to the small signal Desired Layer 1 – Power components Layer 2 – GND plane Layer 3 – Small signal Layer 4 – Small signal / controller GND plane separate the small signal and forms a mechanical bulk cap with the Power layer TI Information – Selective Disclosure

6-Layers PCB Desired Undesired Layer 1 – Power components Layer 2 – Small signal Layer 3 – GND plane Layer 4 – DC power / GND plane Layer 5 – Small signal Layer 6 – Power components / controller Desired Layer 1 – Power components Layer 2 – GND plane Layer 3 – Small signal Layer 4 – Small signal Layer 5 – DC power / GND plane Layer 6 – Power components / controller DC power and GND planes work as reference planes in AC In a multilayers PCB the GND plane should not be fragmented TI Information – Selective Disclosure

Layout guidelines for the Power Management The origins of the noise Reccomended layout per topology Real life example Reccomended layers stack-up Land patterns of power components TI Information – Selective Disclosure

Land patterns of power components TI Information – Selective Disclosure

Connecting Bypass Capacitors Connecting to high frequency bypass caps: This assumes a connection into internal planes Terrible! Long thin traces add inductance and effectively isolate the capacitor Keeping vias close to pads minimizes parasitic inductance Doubled vias further reduce inductance This technique further reduces inductance by reducing the high frequency loop area Good Better Best Super!

Connecting Bypass Capacitors TERRIBLE GOOD

Thank You! Questions?