Summary of the parallel session. Design and organisation Summary of the parallel session. Design and organisation. Moving towards the TDR … Dominique Breton SuperB meeting – La Biodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Agenda of the electronics parallel session SVT: Giuliana Rizzo DCH: Giuseppe Finocchiaro PID: Jerry Va’vra EMC: Dominique Breton IFR: Angelo Cotta Ramusino Trigger/DAQ: Dominique Breton & Gregory Dubois-Felsmann Radiation topics: Dominique Breton Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Subsystems status SVT: Work is mostly concentrated on the successful detector R&D L1 buffers could be implemented on the HDI Time-stamped readout should fit with any DAQ scheme DCH: Goal is to shorten the signal shape Request for background level in the chamber and radiation level at the electronics location Frascati engineers will join soon but there is a call for more manpower PID: R&D is going on with fast detectors and analog memories For the barrel, they could be used to store the signal shape of 64-channel MAPMTs For the forward PID, they could be used for both TOF or FARRICH with MCPPMTs (or SiPM) and digital post-processing in order to precisely interpolate the arrival time of the signal EMC: Goal is to shorten the signal (both in preamps and digital filtering) from barrel CSI crystals. Forward may use faster LYSO crystals with APDs Backward may use fast tile/fiber/SiPMs and could thus help for backward PID IFR: R&D ongoing with fiber/SiPM readout Time measurement based on multiple threshold crossing and digital interpolation Electronics based on TDC in VME crates with fast interconnections for trigger Dominique Breton – SuperB meeting – LaBiodola – June 2008

A few remarks about DAQ to FEE … It would be nice to keep the BABAR philosophy : “Global” and “Local” commands are sent on an unique bidirectional link. Their length could go up to 32 bits with new Gbit links. FCTS-to-ROM L1 commands are a bottleneck for the L1 accept : this could be solved by using 2.5Gbits/s serializers links for FCTS-to-ROM links. The L1 trigger latency will probably remain variable (due to the lack of time precision of signals implied in the decision) New problems with high occupancy in SuperB : pile-up when signal shape is too slow => could be solved with variable window length overlapping of trigger windows with closer triggers => easy to deal for FEE With the radiation, the smaller = the better for the FEE buffer size. Reducing L1 trigger latency should be possible with modern electronics. The Read_event command is it still necessary ? Gregory put an updated version of his slides on the parallel session agenda. It addresses all the points raised here above. FCTS/DAQ to FEE architecture could actually get somehow closer to that of LHC experiments … Dominique Breton – SuperB meeting – LaBiodola – June 2008

Example of possible SuperB implementation FCTS Max jitter << 100ps & no phase spread 60MHz clock L1 accept 2.5Gbits/s Optical links Read event ROM FEC 60MHz clock ? L1 accept DAQ Read event Setup and control 16 Setup and control 1 32-bit command word every clock cycle Subsystems control Same command word serialized at 60MHz (dedicated or broadcasted) Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Summary of main points (1) Trigger and DAQ: Need of a fully triggered system, including EMC Aim at getting L3 and maybe even L1 track information from SVT Event size has to be kept reasonable (mainly dependent on background and new subdetectors) Some intelligence is necessary on the detector in order to cope with the high data and trigger rates. Whatever it is has to be remotely and safely reprogrammable. Precise requirements for the L1 trigger have to be defined. This has an influence over the whole system design. L1 central Trigger hardware is an electronics subsystem by itself: we need candidates to take care of it ... Based on all the discussions which occurred, a note is being prepared by Gregory and Stephen to propose updated DAQ to FEE requirements DAQ and subsystems: The optical link looks like a natural physical separation between them We could however imagine that DAQ- and FCTS-linked common elements could be considered as part of DAQ on the detector side Their physical implementation could be either in charge of subsystem groups and reviewed by DAQ experts (BABAR like), or designed by DAQ experts and used like an IP inside programmable digital electronics inside subsystem design. Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Summary of main points (2) FCTS : Mixing of clock and data in the same link is a source of jitter for the recovered clock Moreover, the phase difference between input and output of commercial fast deserializers may not be constant (different @ each power-up: due to internal PLLs – not true with Glink) Available gigabit transceivers have to be tested This solution may anyway most probably be inadequate for ps-sensitive detectors Use of crystal-based jitter cleaning PLLs might be a solution if the problem is only the deterministic jitter Otherwise, a dedicated clock distribution scheme has to be foreseen … Common design: Parts of detector-sided electronics design may be common if necessary in case of global common needs This is especially true for FCTS and DAQ linked elements Fast analog memories could also be good candidates to be used on most detectors Interaction has to be maximum between subsystems in the requirement definition phase Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Summary of main points (3) Radiation: Simulations have to be performed, especially for neutron flux (if feasible, a flux map would be of great help) Mitigation methods including choice of components will depend on the results. Localization of sensitive electronics on the detector may also depend on these flux Reuse of BABAR elements: BABAR’s dismantling will begin next July. Beside inner calorimeter electronics, are there items worth being kept for SuperB ? It was shown yesterday that the distance between SuperB and its electronics hut shouldn’t be too much longer than BABAR’s Could some cables get reused ? Crates ? Power supplies (LV and HV) ? For instance, the DIRC HV supplies and their expensive cables might be good candidates Same for calorimeter power supply cables Reuse of optical fibers doesn’t seem very appealing Experts from BABAR subsystem should prepare lists of items and get in touch with Bill before October. Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Electronics organization (1) Like in BABAR, it would be wise to group all of the following in a single working group: Front-end electronics Data acquisition (and dataflow software) Trigger (including Level 3 Trigger) Electronics for detector controls Electronics infrastructure Each subsystem has at least a representative attending the meetings of this group. Each of said subgroups concentrates in its work area. This comprehensive group has to worry about: The conception of the system design The writing of the TDR Setting up the reviews during the design cycle Sharing solutions between subsystems Pushing subsystems to help each other out during design and implementation Affording the flexibility to redeploy resources Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Electronics organization (2) Reviews are a key point (with the participation of experts from other subdetectors): particularly to cover interfaces for sharing the knowledge and experience between groups for making the design effort more harmonious We should institute a series of design reviews for each component or subsystem: PDRR+CDR: Preliminary Design Requirements Review & Conceptual Design Review Held before detailed design begins. Reviews requirements and whether conceptual design addresses requirements. PDR: Preliminary Design Review Held following completion of detailed design and before fabricating prototype. A detailed review of interfaces and schematics. Also results of partial prototypes. FDR: Final Design Review Held following completion of prototyping and system tests and before production fabrication. Focuses on completeness and results of testing (measured against requirements). Also reviews plan for acceptance testing of production units Reviews have to be tied to milestones, attended by physicist from the concerned subsystem, engineers from other subsystems, and external members. This ensures the best brainstorming and feedback efficiency Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 System design (1) Defining requirements is essential right now. A wide interaction between engineers and physicists is mandatory. Requirements should be realistic in terms of system complexity: Why should we take undue technical risk (and hence cost & schedule risk)? On the other hand, we’ve to try to foresee all the possible contingency … We have to do the overall system design first. This is not obvious since it may depend on criteria we don’t yet master Simulations should play an eminent role there We have to make certain that all subsystems buy into the common solutions, yet give them flexibility in the detailed implementation. Acceptance is important to the completeness and success in the implementation. It should be achieved by involving the entire community in the development of the protocols and standards. Flexibility in detailed implementation. Allows subsystems to adapt protocols and standards to the details of their system. Allows subsystem designers to take ownership of their subsystem. Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 System design (2) We should not always follow standard approaches or architectures. We first have to understand our requirements the best we can. Then to take advantage of everyone’s experience to optimize our own system design. We have to pay attention to all aspects of the system during the design phase, not forgetting: Power supplies & power distribution. Cabling. Cooling. And, of course, Grounding & Shielding This is not a negligible amount of work … When drawing up our schedule, we should plan backwards from the earliest date that the electronics could be used by the detector. Then we conservatively schedule time for commissioning, installation, testing, production, and prototyping. Then we add some contingency. All the remaining time (if not negative), we allow for design. Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Towards the TDR We would like to have the TDR ready within two years from now. The architecture of all the subsystems electronics has to be clearly defined ahead. Both the subdetector specific and the common solutions have to be described ASIC requirements and global architecture have to be defined Alternate solutions can be described, but a baseline must be chosen Cost must be estimated as sharply as possible, including prototypes TDR writing also relies on electronics groups. Electronics meetings have to take a growing place during the SuperB collaboration meetings Electronics groups organization should be set up soon. We have to specify the constraints on the DAQ and trigger sides of subsystems electronics as early as possible We have to pay attention to all formerly quoted aspects of the system while preparing the TDR, trying to normalize: Power supplies & power distribution. Cabling. Cooling. Grounding & Shielding Radiation mitigation policy is also a main subject, shared between all subsystems. Dominique Breton – SuperB meeting – LaBiodola – June 2008

Dominique Breton – SuperB meeting – LaBiodola – June 2008 Conclusion Since last workshop, we moved forward a better understanding of the physics requirements and their consequences on electronics design: Evolving from BABAR, a new set of requirements for the DAQ to FEE architecture will be proposed soon Subsystems already started thinking of how to cope with these requirements Radiation problems are also taken into account, even if we do not have a clear idea of how bad the situation will be Having a safe design with little radiation is harder but fine … The opposite is a catastrophe ! In order to be able to write down the TDR, we need some R&D and simulations on a few key points: Simulations of the different DAQ front-end architectures Simulations of the radiation background on the detector Jitter after clock recovery and phase spread in available Gigabit transceivers. Electronics groups have to be set up soon. They have a big role to play in the TDR writing. A lot of talented engineers are therefore needed in the near future. We should discuss electronics in the bi-weekly phone meetings, both on a regular basis (once a month ?) and whenever necessary. Dominique Breton – SuperB meeting – LaBiodola – June 2008