Sassan Tabatabaei, Freddy Ben-Zeev and Michael Lee

Slides:



Advertisements
Similar presentations
University Missouri Rolla
Advertisements

11/11/02 IDR Workshop Dealing With Location Uncertainty in Images Hasan F. Ates Princeton University 11/11/02.
August 2004Multirate DSP (Part 2/2)1 Multirate DSP Digital Filter Banks Filter Banks and Subband Processing Applications and Advantages Perfect Reconstruction.
Copyright 2001, Agrawal & BushnellVLSI Test: Lecture 181 Lecture 18 DSP-Based Analog Circuit Testing  Definitions  Unit Test Period (UTP)  Correlation.
Chapter 9 High Speed Clock Management. Agenda Inside the DCM Inside the DFS Jitter Inside the V5 PLL.
Peak Distortion ISI Analysis
Propagation Characteristics
Outline Transmitters (Chapters 3 and 4, Source Coding and Modulation) (week 1 and 2) Receivers (Chapter 5) (week 3 and 4) Received Signal Synchronization.
Computer Networks Chapter 3: Digital transmissions fundamentals Part 1.
Spread Spectrum Techniques
Lecture 1 Signals in the Time and Frequency Domains
Technion – Israel Institute of Technology Department of Electrical Engineering Winter 2009 Instructor Amit Berman Students Evgeny Hahamovich Yaakov Aharon.
DOLPHIN INTEGRATION TAMES-2 workshop 23/05/2004 Corsica1 Behavioural Error Injection, Spectral Analysis and Error Detection for a 4 th order Single-loop.
Understanding ADC Specifications September Definition of Terms 000 Analogue Input Voltage Digital Output Code FS1/2.
2.5Gbps jitter generator Part 1 final presentation.
Genuine random number generator demo software explanation What happens in this demo LeTech Co.,ltd.
MAY T10/08-248r0 Considerations for Testing Jitter Tolerance Using the “Inverse JTF” Mask Guillaume Fortin PMC-Sierra.
Testing OIF Optical and Electrical Implementation Agreements Gary Goncher Tektronix, Inc.
Jitter Experiment Final presentation Performed by Greenberg Oleg Hahamovich Evgeny Spring 2008 Supervised by Mony Orbah.
Wireless Communication Technologies 1 Phase noise A practical oscillator does not produce a carrier at exactly one frequency, but rather a carrier that.
The Physical Layer Lowest layer in Network Hierarchy. Physical transmission of data. –Various flavors Copper wire, fiber optic, etc... –Physical limits.
OFDM Each sub-carrier is modulated at a very low symbol rate, making the symbols much longer than the channel impulse response. Discrete Fourier transform.
- 1 - YLD 10/2/99ESINSA Tools YLD 10/2/99ESINSA Filters Performances A filter should maintain the signal integrity. A signal does not exist alone.
Physical-layer Identification of UHF RFID Tags Authors: Davide Zanetti, Boris Danev and Srdjan Capkun Presented by Zhitao Yang 1.
Capacitive transducer. We know that : C=kЄ° (A/d) Where : K=dielectric constant Є° =8.854 *10^-12 D=distance between the plates A=the area over lapping.
Adaphed from Rappaport’s Chapter 5
Presented by: Sergey Volkovich Vladimir Dibnis Spring 2011 Supervisor: Mony Orbach.
1 Strategies for Coping with Non-linear and Non-time Invariant Behavior for High Speed Serial Buffer Modeling Richard Mellitz Results from DesignCon2008.
ISI Causes and Cures Eye Diagram (means of viewing performance)
Constellation Diagram
Outline Transmitters (Chapters 3 and 4, Source Coding and Modulation) (week 1 and 2) Receivers (Chapter 5) (week 3 and 4) Received Signal Synchronization.
High-Speed Serial Interface Test in Production Assure Device Interoperability In Real-World Environments.
MULTICARRIER MODULATION FOR DATA TRANSMISSION. INTRODUCTION Modulation techniques: improve the efficiency of transmitted power. Linear equalization of.
Crashcourse Oscilloscope and Logic Analyzer By Christoph Zimmermann.
Mobile Radio Propagation - Small-Scale Fading and Multipath
CAUI-4 Chip – Module Draft Baseline
The Search for Accurate CDM Waveforms
Flexible FPGA based platform for variable rate signal generation
Defining serial links for SuperB
Data transmission characterization with underwater copper link
High-Speed Serial Interface Test in Production
Dynamic Specifications
Analog to digital conversion
Sassan Tabatabaei, Freddy Ben-Zeev and Michael Lee
Receiver Performance & Characteristics
Sampling rate conversion by a rational factor
ECE 546 Lecture - 23 Jitter Basics
Digital Acquisition of Analog Signals – A Practical Guide
Sampling Theorem told us …
Signals and Systems Networks and Communication Department Chapter (1)
Channel Estimation 黃偉傑.
Channel Estimation in OFDM Systems
Unit 44 Vibrationdata Sine Filtering.
Telecommunications Engineering Topic 2: Modulation and FDMA
Predicting Every Spike
Advanced Jitter Analysis
UWB Receiver Algorithm
Finite Wordlength Effects
Basic Image Processing
Radio Propagation Review
DEPARTMENT OF INFORMATION TECHNOLOGY DIGITAL SIGNAL PROCESSING UNIT 4
XMBTM Product 10 Gbps Backplane using Multiwire ® Technology
Fast and Slow Contrast Adaptation in Retinal Circuitry
Finding Periodic Discrete Events in Noisy Streams
PHY Abstraction based on PER Prediction
Lecture 17 Analog Circuit Test -- A/D and D/A Converters
Serial, Covert Shifts of Attention during Visual Search Are Reflected by the Frontal Eye Fields and Correlated with Population Oscillations  Timothy J.
DEPARTMENT OF INFORMATION TECHNOLOGY DIGITAL SIGNAL PROCESSING UNIT 4
Channel Estimation in OFDM Systems
Lecture 22: PLLs and DLLs.
Presentation transcript:

Sassan Tabatabaei, Freddy Ben-Zeev and Michael Lee Jitter Generation and Measurement for Test of Multi-gigabit Serial Interconnects Sassan Tabatabaei, Freddy Ben-Zeev and Michael Lee

Purpose RJ, DDJ, and PJ injection for receiver test Use delay line modulation Programmable DDJ Jitter measurement methodology with continuous TIA (CTIA) Markerless measurement Objectives: To inject jitter in data streams for jitter measurement verification and receiver testing with: Programmable RJ Programmable high and low frequency PJ Programmable DDJ Discuss continuous time interval analyzers and how they can measure jitter without any marker signal ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Outline Jitter injection issues Programmable jitter injection Continuous time interval analyzer (CTIA) Markerless and fast RJ/DDJ measurement methodologies ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Typical setup (e.g., XAUI) Jitter Injection Typical setup (e.g., XAUI) Typical jitter injection setup includes: Pj injection through PM/FM modulation of RJ generators (limited in frequency and range) RJ through amplitude superposition (sensitive to rise/fall time and glitches) DDJ: fixed application-specific filters ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Jitter Injection Limited PJ frequency range Large RJ may cause spurious edges DDJ programmability very limited Requires filter tuning Typically not portable across applications with different bit rates ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Jitter Injection Programmable setup NEW Info Proposed method. Use delay line phase modulation in a phase-locked system NEW Info ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

DDJ Injection DDJ injection setup ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Traditional Time Interval Analyzer (TIA) Operation Principles Traditional TIA architectures ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Traditional Time Interval Analyzer (TIA) Operation Principles Traditional TIA architectures with marker signal ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Continuous Time Interval Analyzer (CTIA) Operation Principles Continuous TIA operation Tracking edge timing relative to a common reference continuously ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Continuous Time Interval Analyzer (CTIA) Operation Principles CTIA does not require any marker! TO demonstrate examples in RJ/DDJ measurement methods. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Jitter Measurement Definitions Random jitter (RJ) Uncorrelated to Known sources Gaussian distribution Data-dependent jitter (DDJ) Inter-symbol interference Duty-cycle distortion Reflections Definitions Objectives: To inject jitter in data streams for jitter measurement verification and receiver testing with: Programmable RJ Programmable high and low frequency PJ Programmable DDJ Discuss continuous time interval analyzers and how they can measure jitter without any marker signal ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Jitter Measurement Definitions Time Interval Error (TIE) function: Ideal signal Real signal ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

RJ Measurement Data signal with a repeating pattern (K28.5 in this example) ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

RJ Measurement TIE measurement for the same edge of the pattern ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

RJ Measurement Sampling the same pattern edge: DDJ deconvolution Uniform sampling of edge deviation sequence. Good for FFT. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

RJ Measurement TIE TIE FFT Time (s) Normalized frequency 0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09 -100 -50 50 100 Time (s) TIE sequence (ps) TIE 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 10 -4 -2 2 Normalized frequency Scaled FFT (ps) TIE FFT FFT deconvolves PJ ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

RJ Measurement Frequency domain deconvolution Insensitive to PJ and DDJ Predictable Repeatability 3% for 8192 samples No external marker required ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

DDJ Measurement DDJ: set event counter to walk over pattern edges multiple times (virtual marker!). ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

DDJ Measurement Histogram for each pattern edge Edge 5 Edge 4 Edge 2 -40 40 80 120 20 60 100 TIE (ps) Bin population Histogram for each pattern edge Edge 1 Edge 2 Edge 3 Edge 4 Edge 5 Separate TIE for pattern edges. Measure DDJ. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

DDJ Measurement Time domain deconvolution Per-edge time shift measurement Insensitive to RJ and PJ (averaging) No external marker required ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Example: Sinusoidal DDJ DDJ Injection Example: Sinusoidal DDJ 15 CTIA (GT 4000) Scope (86100C) 10 5 Edge shift (ps) Example of DDJ injection performance. -5 -10 20 40 60 80 100 120 Transition bit number ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Measurement Results (RJ) Accuracy 20 22 24 26 28 30 32 3 4 6 8 10 RJ (ps) CTIA TDS7404 Linear fit -0.5 0.5 D Noise generator attenuation (db) RJ is accurate within 0.5ps. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Measurement Results (RJ) Immunity to DDJ 2.5Gbps, PRBS7 pattern 20 25 30 35 40 5.4 5.5 5.6 5.7 5.8 RJ (ps) Injected DDJ (ps) RJ is immune (insensitive) to variations of DDJ. Maintain accuracy for different jitter profiles. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Measurement Results (DDJ) Accuracy 50 45 40 PRBS7 35 30 Measured peak-to-peak DDJ (ps) K28.5 25 DDJ accuracy (within 3ps) CTIA 20 ET-DSO 15 10 20 40 60 80 100 120 140 160 AWG amplitude (mV) ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Measurement Results (DDJ) Immunity to RJ and PJ 2 4 6 8 10 12 32 33 34 35 Measured peak-to-peak DDJ (ps) Injected RMS RJ (ps) 50 100 30 31 32 33 34 Injected PJ (ps) Measured peak-to-peak DDJ (ps) DDJ injection and measurements immune to RJ and PJ. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects

Conclusions Delay line modulation with locked AWG provide flexible and programmable jitter injection method. No need for application-specific DDJ filters CTIA: markerless jitter separation Virtual marker Accurate Fast: No marker generation time Compact data volume Completely programmable jitter injection method including DDJ introduced. CTIA perform jitter decomposition without any marker signal. ITC 2004 Jitter Models & Measurement for High-Speed Interconnects