Short Pulse Reading for STT-RAM fren@ee.ucla.edu

Ferro-magnetic layers Background STT-RAM Storage element: MTJ Represents “0/1” by the configuration of magnetization direction Read/Write operations: CMOS circuits CMOS and MTJ variability are increasing Resulting in more stringent constraints on CMOS design Parallel Anti-parallel Low RP - ”0” High RAP - ”1” Ferro-magnetic layers In STT-RAM MTJs are the storage elements. And read write operations are carried out by CMOS devices. So circuit design techniques are essential for extracting the best performance, energy and area efficiency for STT-RAM. The bottom figure shows the typical switching char. of MTJ device. For a certain switching probability, I is a f of the T. To be brief, the goal of the R/W circuit design is to make sure that in the worst case, W circuit would still operates MTJs in the red region, where it has 100% sp, read circuit has to operate MTJs in the blue region, where MTJs won’t be overwritten during the read. However, not easy.

Read Circuit Design Sense the RMTJ (RAP / RP) through IREAD Without disturbing the cell (0% switching prob.) Two ways to get 0% switching probability Low current reading (LCR) Short pulse reading (SPR) Write (2) Short Pulse Reading (1) Low Current Reading Read

2 ways to get 0% switching prob. Read Circuit Design JC scaling will eventually create difficulty for LCR How to implement SPR? What is the circuit structure? Write (2) Short Pulse Reading (1) Low Current Reading Read 2 ways to get 0% switching prob.

How to implement SPR? When can we turn off sensing circuit? When a safe read margin (VMTJ-VREF > VOS_latch + NM) is established VOS_latch < 15 mV How fast that read margin can be established? The best SPR circuit should be able to establish the largest read margin with the least time.

#1: Current-Mirror Sense Amp (CMSA) Current Sensing Speed is limited by the IMTJ VMTJ is fixed, between VMTJ_P and VMTJ_AP VMTJ-VREF is limited [1] D. Gogl, et al., JSSC, Vol. 40, No. 4, Apr. 2005 [2] J.P. Kim, et al., VLSI, 2011 [3] J. Kim, et al., JVLSI, 2011

#2: Split-Path Sense Amp (SPSA) Current Sensing Speed is limited by the IMTJ VMTJ is reverse to VMTJ Larger VMTJ-VREF [1] S.O. Jing, et al., US Patent, Pub. No. US 2010/0321976 A1

#3: Body-Voltage Sense Amp (BVSA) Body Voltage Sensing Body-connected load is better than diode connected load Speed is no longer limited by IMTJ VMTJ is reverse to VMTJ Even larger VMTJ-VREF Benefiting from gain of the sense amp [My proposal]

RM Definition RMP = μ(VMTJ,P − VREF,P) + 3σ(VMTJ,P − VREF,P) should be < 0 RMAP = μ(VMTJ,AP − VREF,AP) − 3σ(VMTJ,AP − VREF,AP) should be > 0 +3σ -3σ RMP RMAP

RM and performance Comparison We compare 3 sensing circuits at ISO reading current: #1: Current-Mirror Sense Amp (CMSA) Qualcomm design [VLSI’11] #2: Split-Path Sense Amp (SPSA) Qualcomm design [US Patent 2010/0321976 A1] #3: Body-Voltage Sense Amp (BVSA) UCLA proposal to demonstrate the read margin and speed advantage of our approach Current sensing Voltage sensing

Simulation Setup MTJ CMOS Size: 40x100 nm RA = 9 Ω∙um2, TMR = 110%, Rp = 2.9 kΩ Iread,P ~ 50 uA, Iread,ap ~ 30 uA 5σ MTJ variation 1 σRA = 4%, 1 σTMR = 5% CMOS 65-nm Process Variation Chip-to-chip + across chip local variation (ACLV) Monte Carlo Run # = 5000 Temp and VDD are kept the same in comparison room temp VDD = 1V

IMTJ Distribution CMSA SPSA BVSA (uA) CMSA SPSA BVSA μ (IMTJ,P) 36.5 49.1 53.5 σ (IMTJ,P) 2.61 3.19 3.16 μ (IMTJ,AP) 26.9 31.4 33.5 σ (IMTJ,AP) 2.08 2.27 2.17

SMTJ − SREF Distribution SPSA BVSA

VMTJ and VREF Distribution CMSA SPSA BVSA After VMTJ and VREF are settled

VMTJ − VREF Distribution and RM CMSA SPSA BVSA After VMTJ and VREF are settled (mV) CMSA SPSA BVSA RMP −268 −596 −829 RMAP 303 432 696

RM vs. Sensing Time (Pulse Width) Write Read Sensing time (ns) required to achieve a given RM RM (mV) CMSA SPSA BVSA 100 2.17 1.94 0.60 200 3.54 2.80 0.67 300 N/A 3.84 0.74 400 5.78 0.82 500 0.93 600 1.25 650 1.58 700

Summary and Conclusions Methodology: Proposed body-voltage sense amp (BVSA) reading circuit is compared with two existing current-sense reading circuits. Read margin and sensing time are compared at the same reading current. Observations: Our circuit shows the biggest read margin > 400 mV improvement as compared CMSA > 250 mV improvement as compared to SPSA Our circuit achieves high read margin with much shorter pulse width (sensing time)