Verilog Introduction Fall 2004-2005

Module module <module-type> (<ports>); <components> endmodule

Module module myadder (Cout, Sum, a,b, cin); input [3:0] a,b; input cin; output [3:0] Sum; output cout; <components> endmodule

Structural code Behavioral code Ex1: module mynand (x, a, b); input a, b; output x; wire x,y; and A1 (y,a,b); not A2 (x,y); endmodule Ex2: module mynand (x, a, b); input a, b; output x; wire x,y; assign y = (a==1 & b==1)?1:0; assign x = (y==0)?1:0; endmodule

Components Definitions Declarations Procedural assignments Parameters Nets Registers Tasks and functions Declarations Primitives and Instances Continuous assignments Procedural assignments One pass Cyclic

Parameters Used to define constants e.g: parameter width = 8;

Nets Used to connect components Are driven and can change at any time. Types: wires, wand, wor, supply0, supply1 E.g.: wire x; wire [width-1:0] a, b; //both a and b are buses

Registers Used to hold values. Can change only at discrete time. Types: reg, integer, time, real e.g.: reg r1, r2; reg [width-1:0] r3;

Primitives basic logic gates and, or, not, xor …. Pre-defined User-defined primitives are also possible. The order of the ports is fixed. nand A1 (<output>, <input1>, <input2>, <input3>,….);

Tasks/functions Used to organize code Functions - encapsulate combinational logic. Tasks – can encapsulate sequential logic.

Continuous assignments Data flow between wires and registers. Express combinational logic. Data “propagates” through the wires. Not executed in source order. “net” is always the LHS of a CA e.g. wire x; assign x = (a==b)?1:0;

example wire x, y; //In response to a change in either “a” or “b” assign x = (a==b)?1:0; //x changes first assign z = (y==0)?1:0; //z changes third assign y = (x==1)?1:0; //y changes second

Procedural blocks Represent both combinational and sequential logic. More than one procedural block. All run concurrently. Within a block, can be concurrent or sequential. LHS must always be a register. Two types: One pass: initial Cyclic behavior: always

One Pass A single block of statements. Executed just one time. Begin at time 0. Use of the keyoword: initial e.g.: reg x; initial x = 0;

example initial begin x = 1; y = f(x); #1 x = 0; //After a delay of 1 time unit y = f(x); //Sequential behavior. end

Cyclic behavior Begin at time 0. Executed a number of times. Event driven. Use of keyword: always Can be blocking (sequential execution) or non-blocking (non-sequential execution). e.g.: always #10 clock = ~clock;

Example of combinational logic //nand operation reg x, y; always @ (a or b) begin //x =~y; //If this statement is present, then x will be evaluated first //and the code will not give the expected behavior. if(a & b) //As it is, y will be evaluated first, followed by x. y = 1; else y = 0; x = ~y; end

Example of sequential logic //shift register reg a,b; always @ (posedge clock or posedge reset) begin if(reset) begin a =0; b=0; end else a = b; //Shift the value of b to a b = c; //Shift the value of c to b end end // behavior is different if we switch // the two commented statements.

Blocking assignment Consecutive statements are blocked until the current statement is evaluated (sequential evaluation). Use of “=“. Previous example Preferred usage for combinational logic, where the data must propagate.

Non-blocking assignment Ex. 5: reg a,b; always @ (posedge clock or posedge reset) begin if(reset) begin a =0; b=0; end else a <= b; //Shift the value of b to a b <= c; //Shift the value of c to b end end // behavior is the same even if we // switch the two statements.

Non-blocking assignment All the statements are executed in parallel. Use of “<=“ Preferred usage for sequential logic.

To do Include a Verilog file in a project. Examples 1 to 5, create Verilog files and simulate them.