AHCAL Detector Interface electronics

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Presentation transcript:

AHCAL Detector Interface electronics AIDA 2020 first annual meeting, WP 14.4 New DIF Jiri Kvasnicka DESY Hamburg 14.6.2016

AHCAL Interface electronics Controls and reads up to 3 SLABs with 6 HBU each Major redesign of DIF (originally NIU) Redesign of POWER4, CIB (Central Interface Board) New production of CALIB2 Redesign driving forces: We had to replace the old FPGA (Spartan3) Better power pulsing

DIF2 Major redesign Zynq 7020 FPGA DDR3 memory (not used yet) Mini-USB (moved from CIB) Boots from: JTAG (volatile) QSPI FLASH (non-volatile) µSD-card (non-volatile) – works only when DDR3 memory is on Different voltages produced from 3.6V input: 3.3V, 2x2.5V, 1.8V, 1.0V, OC: 1.2V, DDR3: 1.35V and 0.65V 5V from POWER4 for USB. Current consumption (everything on): 1.3A (~5W). Without DDR3: 1A (~3.6W)

DIF2 Firmware Only FPGA part of ZYNQ used Changed design tool flow (ISE 14.7 → Vivado 2015.4) FW based on previous DIF Different clock distribution (Spartan3 vs. Artix7 resources) New commands for voltage control (incompatible with old DIF) First version worked out of the box => we could test all the functionalities before larger DIF2 production Firmware not final! Unconstrained timing => many timing violations Too much asynchronous logic Major code review and retiming needed

POWER4 board Takes +4V, +12V, SiPM-Bias No +6V any more Power dissipation significantly reduced! Power pulsing improved due to bigger capacitors Independent switching of voltage groups (matches new DIF) Improved software controlled adjustment of SiPM bias voltages

Cooling scheme Hot spots have a thermal contact to a copper cooling plate on top

Commissioning results Beam test @ DESY 1 bug if firmware fixed stable afterwards Test of power-pulsing (single HBU) no visible degradation of SPS from “MIP” Check of the timing of DIF2 (using external time reference – BIF) no difference from old DIF

Summary New interface electronics delivered DIF2 firmware adopted from old DIF to a new FPGA Commissioning successful Roadmap: Q3 2015: Delivery of 4 DIF2 boards and 14 CALIB boards Q4 2015: POWER4 boards and CIB delivered Q1 2016: firmware for DIF2 ready, start of commissioning Q2 2016: beam test @ DESY Q3 2016: expected new batch of DIF2, POWER4, CALIB and CIB boards