INSTRUMENT DATA PROCESSING UNIT (IDPU) Mission Critical Design Review Michael Ludlam University of California - Berkeley

Overview Instrument Overview, Block Diagram and Board Status Power Interface, supply switching Data Interface, TM & TC. Operational Modes Flight Software Data Rates and Storage Grounding Diagram Harness Diagram Mass & Power Mechanical ICDs GSE ETU and FM Test Plans Safety / Contamination RFA Responses Schedule

IDPU Box

IDPU Core Functions IDPU Core Functions Instrument signal processing and formatting into CCSDS packet frames Instrument state of health data collection and formatting Instrument data memory storage Instrument data compression Instrument power conversion and regulation Instrument power switching Actuator (Booms, Doors, Attenuators) control Spacecraft Data and Power Interface IDPU Reviews (Instrument Board Reviews were presented at Instrument CDRs) IDPU CDR 20th April 2004 FGM CDR 6th April 2004 SCM CDR 8th April 2004 SST CDR 19th April 2004 ESA CDR 19th April 2004 EFI CDR 20th April 2004

IDPU Team IDPU Core Systems Data Controller Board DCB Dorothy Gordon UCB Power Control Board PCB Craig Domeny, UCB Low Voltage Power Supply LVPS Peter Berg, UCB Flight Software Frank Harvey, UCB Mechanical Heath Bersch, UCB IDPU Instrument Boards DAP Ron Canario, UCB BEB Hilary Richard, UCB DFB Aref Nammari, LASP ETC Rob Abiad, UCB FGE Uli Auster / Werner Magnes, TUBS IDPU Support Functions IDPU Lead: Michael Ludlam, UCB Thermal: Chris Smith, UCB Ground Support Equipment: Jim Lewis, UCB. Reliability and Quality Assurance (R&QA): Ron Jackson, UCB Parts Engineering: Jorg Fischer, UCB

Block Diagram

IDPU Board Status IDPU Core Systems DCB 3 ETUs built, 2 at UCB for interface and software testing. PCB PCB ETU in population . LVPS ETU in fabrication. Flight Software Phase I and Phase III nearly complete. Mechanical ETU housing machined, Vibration completed. IDPU Instrument Boards DAP Revised ETU in fabrication, Original ETU in testing. BEB ETU tests on going. DFB Breadboard delivered to UCB. ETU ready for fabrication. ETC ETU tests on going. FGE ETU built and testing on going. PCB/FGE board in population.

Instrument Power Interface Probe provides Instrument package with 28V through the IDPU. This is nominally 22-34V. Instrument Supply interface is at LVPS. Produces 32 voltages Primaries are current limited Topologies chosen to promote efficiency DC-DC converter frequencies run over 100kHz to avoid science bands. Supplies are soft started to minimize turn-on stresses – input current controlled Regulation – 1% on directly regulated voltages and 5% on auxillary voltages Isolated secondaries where appropriate Impedance: < 500 milliohms DC-10KHz effective line impedance in the service at the instrument connector Grounding: 28V service load shall return its current through the provided return line. The 28V return shall be isolated from signal and chassis ground by at least 1 Mohm and no more than 1F. Inrush and Transients: <10A for 1 msec; < Peak power consumption after 10ms Motor & 28V Actuator Supply interface is at PCB. Voltages are switched on the PCB through board FPGA by command. Heater Supply interface is at PCB Voltages are routed through board to instrument heaters.

Power Distribution

Instrument Switching Services All power switching is controlled by command to PCB. One switch enables the supply (e.g. +2.5VD) One switch enables supply to instrument (e.g. FGM +2.5VD) Supply switches have voltage and current monitors Supply will trip in an over current condition Tripped supplies can be reset on, or forced on by command Switches are controlled by Actel FPGA on PCB which responds to commands from the DCB.

Actel Issues Themis uses 11 RT54SX72S Actel FPGAs – 9 of these are in the IDPU. There are a number of issues with this family of Actel that have been well documented by GSFC and Actel – most notably ground bounce, antifuse programming failure and output transients or “burps”. To mitigate risk the following steps are being taken; Internal Review of FPGA VHDL/Schematic Designs amongst Themis FPGA engineers. Distribution of Actel design best practice document to engineers drawn from experience and documentation. External Review of board layout, best design practices by Actel. Use new programming algorithm for Silicon Sculptor. Power switches designed to turn on 2.5V before 5V. UCB in consultation with Actel and GSFC experts about current best design practices and solutions to issues.

DCB Board

BAU Interface Command Interface Telemetry Interface 38.4kbaud single line. IDPU receives synchronisation command once per second. Includes probe status segment and command segment. Telemetry Interface Low Speed Telemetry – 38.4kbaud single line. Sent once per second to BAU Includes State of Health packet, Memory Dump or FGM data High Speed Telemetry – 2Mbs, sent in CCSDS formatted packets. Flow of data is broken into fixed length frames.

High Speed TLM Interface High Speed Telemetry Interface Bit serial interface used to send full CCSDS telemetry frames from the IDPU to the spacecraft Bus Avionics Unit (BAU). Characteristics and Timing shown below  

Timing and Synchronisation Two service signals from the BAU 1PPS (1Hz) Sun Pulse Notes: 1. Minimum width 1ms

Inter Instrument Communication Communication Command & Data Interface (CDI) Developed and used by UCB for previous missions Two line interface, clock (8.38MHz) and data. Commands consist of 24 bits (8 address, 16 command data), a start bit, stop bit and parity bit. FGE data consists of 16 bits, and a start bit. DFB data and ETC data is 24 bits and a start bit, stop bit and parity bit.

IDPU Operational Modes SAFE POWER MODE is entered on reset (power-on), by ground command, or by command from the Probe power system in response to an undervoltage condition Power-on state, saves power and the contents of SRR IDPU Core Systems (LVPS, PCB, and DCB) are powered on All instrument sensors and associate electronics are powered off ENGINEERING MODE is entered by ground command in preparation for early operations (instrument health and safety diagnostics), special case instrument operations (boom deploy, high voltage turn-on), and maneuvers (FGM data for attitude determination) Early operation and maneuver state, provides additional specified data Higher engineering rate and additional telemetry points telemetered Operational only, typically during ground contact LOW POWER MODE is entered by ground command or by automated command by the BAU to the IDPU. Core systems and FGM (used for attitude control) are powered, all other instruments are off. On entering Low Power Mode, the IDPU will automatically power off active instruments (apart from FGM). NOMINAL MODE (Science) is entered by ground command (instruments are powered on one at a time) Normal operating state, full science data collection IDPU Core Systems, instrument sensors and assoc. electronics are powered on Booms are deployed

Flight Software Overview

Memory Resources PROM/EEPROM PROM Functions EEPROM/Uplink EEPROM Load Uplink Support L&EO Functions EEPROM/Uplink One-Time Events Test Programs Initialization Params Science Upgrades RESOURCE USAGE 86% PROM 34% RAM 42% EEPROM 36.5% CPU

Instrument Data Rates

Data Storage and Compression DCB contains 256Mb SDRAM for TM storage. This is sufficient space in memory for 4 day orbit + 1day contingency at a spin period of 2.7seconds. Data compression uses lossless Huffman and Delta Modulation algorithms. Entire memory can be compressed by a factor of 2 in less than 2 hours.

IDPU Grounding

Harness Diagram

IDPU Power IDPU within power budget and has 15% contingency Power Mode usage is Safe 5.9W Engineering and Low Power 6.66W Nominal 10.20W

IDPU Mass Mass margin is only 3% but current estimate is mature enough to be confident IDPU will remain within budget.

ICD Drawing

Mechanical Interface PEM SPACER WEDGE LOC ALUM SHIELD HEAT SINKS D-SUB CONNECTOR WEDGE LOC ATTACHED TO BOX WALL

Ground Support Equipment Each IDPU board will have it’s own GSE to check out boards individually. Once ready for integration, boards will be tested through the DCB with the IDPU GSE. This GSE will follow the IDPU through Instrument Suite and Probe I&T.

ETU Test Plans Functional Tests Interface Tests Test and debug performance against requirements Measure power and electrical interfaces Interface Tests Preliminary interface tests between IDPU boards on going for ETU (DCB to DFB complete). Once boards have completed tests with sensors (DAP, BEB, DFB, FGE) they will be integrated fully with IDPU Core boards (LVPS, PCB, DCB). Flexibility in board test order to help accelerate schedule – e.g. PCB can be integrated with LVPS or DCB first. Once all boards are integrated, all services and modes are checked out as a complete instrument. A subset of these tests will become an IDPU functional test to be run later during instrument I&T. IDPU will undergo 2 cycles of thermal vacuum. Completed IDPU ETU will run interface tests with BAU ETU as soon as possible.

FM Test Plans ETU will be used to test out procedures, practices and organisation for the FM. FM build up and I&T will mirror the ETU. Lessons learnt will be taken from ETU and applied to FM Flight Units will have >100 hour logged test time before delivery to probe integration.

Test Plans Software Development Dedicated DCB board used to develop and test FSW. Enables software development and board tests in tandem. Code will be verified on this test bed before programming of flight units. Software will be tested against software requirements document (THM_FSW_001). Software Acceptance test will be developed to test IDPU models during instrument build.

Assembled Test Flow Assembled IDPU Functional Test Metrology Interface Measurements Vibration with SCM pre-amp and ESA Thermal Vacuum (2 cycles) Bake Out Functional Test IDPU Ready

Safety & Contamination Frangibolts 28V Actuator power enabled before frangibolts are fired. Frangibolts will be fired for a minimum of 20 seconds. ESA HV ESA 28V powered for ESA HV to be enabled (FPGA). If ESA 28V power removed, ESA HV disabled (FPGA). ESA HV enable command requires 16bit code (FPGA). FSW will also make the above checks. Contamination IDPU will be cleaned prior to integration with ESA. A number of parts on the IDPU need to be depermed and tested prior to assembly (mostly mechanical). IDPU resides within probe, so not subject to ESC requriements.

Responses to RFAs RFA-INST-01F RFA-INST-02 List jc and dissipation of Mosfets in IDPU. Check heat sinking on assembly. Response: Listed all Mosfet jc and dissipation. All devices are well within derating guidelines and temperature rise above ambient in all cases is small (<10degrees). A post assembly inspection will be made of heat sinks on PCB. RFA-INST-02 Investigate effect of Actel RT54SX72S output transients on designs. Take appropriate action Response: Consulted with Richard Katz at GSFC. Awaiting his and Actel’s report. An assessment of impact on designs will be conducted during Actel design reviews (before FM layout).

Responses to RFAs RFA-INST-R13 RFA-INST-R15 Document jc of 3D+ SDRAM module used on DCB Response: jc = 250 C/W. The SDRAM 3D+ Module has a peak power consumption of 25mW. Increase in temperature will be 6.25C. RFA-INST-R15 Consider using high fidelity power input for IDPU testing Response: Where appropriate during IDPU testing, simulation of more flight like power supply will be used. An early test with BAU ETU is scheduled.

Schedule Project Milestones – IDPU Ready Dates IDPU ETU 8/12/04 IDPU F1 11/1/04 IDPU F2 11/9/04 IDPU F3 11/16/04 IDPU F4 11/23/04 IDPU F5 11/30/04 IDPU F6 12/7/04

Schedule