A VLSI Full Custom ASIC Front End for the Optical Module of NEMO Underwater Neutrino Detector D. Lo Presti domenico.lopresti@ct.infn.it ON BEHALF OF NEMO COLLABORATION Microelectronics Group Catania Department of Physics and Astronomy Bologna Department of Physics

Neutrino Mediterranean Observatory (NEMO) Telescope layout

SYSTEM REQUIREMENTS Very low power because of the distance from the shore; Only one submarine interconnecting cable to have the best reliability and to simplify the deployment; Flexibility to give the possibility of changing parameters; Very small dead-time to get a good detector efficiency; High dynamic range to fit with different kinds of experiments; Very good accuracy of experimental data; Low cost, if possible! System requirements

PERFORMANCES Not more than 300 mW in each Optical Module (OM); Extensive use of full-custom VLSI devices both for analog and digital parts in the OM; Power dissipation less than 5 kW (500 mW per module); Hardware solution for Trigger; Software solution for coincidences; Dead Time < 0.1%; Input dynamic range >14 bit; Timing accuracy better than 1 ns. Specifications

(1) (2) (1) Pre-analysis and storage Unit Optical Module (OM) (1) (1) Pre-analysis and storage Unit (2) Channels concentration & data compression and packaging Unit Schematic of the Optical module electronics (2)

on chip on LIRA board 16 Bit DPTU FIFO FIFO 16 Bit Counter Counter Est. Reset FIFO FIFO R 16/ 16 Bit 16/ I I O O Counter Counter 20 MHz Load Load Read Read CkI CkI TS TS RTc RTc RFf RFf T&SPC T&SPC NSPE NSPE NSPE NSPE RAdc RAdc Vi Vi Start Start Start Start Control Unit Control Unit ACk ACk Dyn Dyn Dyn Dyn PwD PwD CkO CkO R1 R1 R2 R2 SE1 SE1 SE2 SE2 R/W R/W S S CR CR 200 MHz PLL PLL PwD PwD Ck Ck DPTU CkR CkR CkW CkW R R SE SE R/W R/W Cs Cs ADC ADC SR SR I0 I0 LIRA LIRA Os Os 10/ I I O O Data Pack Data Pack ADS 901 ADS 901 I1 I1 & & Anode 80ns I2 I2 Ot Ot Transfer U. Transfer U. 3x250 channel SCA 3x250 channel SCA 5 Mbit/s 80ns Dynode PM CkR CkR CkW CkW R R SE SE R/W R/W Cs Cs SR SR I0 I0 LIRA LIRA Os Os I1 I1 Ot Ot I2 I2 3x250 channel SCA 3x250 channel SCA on chip on LIRA board

Design Specifications of the blocks (1) LIRA AM Sampling frequency 200 MHz Readout frequency 10 MHz Resolution  9 bit Input Dynamic 2 V Input-Output Offset regulation 3 Input Anode Dinode 20 MHz Master Clock 256 cells

Design Specifications of the blocks (2) T&SPC Trigger unit PMT signals classification 2 thresholds remotely settable by slow control Th1 Trigger SPE/4  Start signal 5 bit Th2 5 SPE  Dynode samples selection 5 bit Valid Time window NSPE 5 bit Classification time 60 ns remotely settable PLL Generation of 200 MHz Slave Clock starting from 20 MHz Master Clock

Optical Module Electronics Working principles The signal coming from the PMT is compared to two Threshold: Th2 = SPEx5 (*): DYN signal. Th1 = SPE/4 (*): START signal; Signal Classification: Delayed START signal ~ 60 ns – Decision Time; More than one hit; Too long (*); Non Single PhotoElectron; (*) Remotely settable by slow Control: DAC 4 bit and latch. 1 The PMT signal causes a trigger event and after ~ 60 ns it is classified. The Control Unit receives the start signal and set one of the LIRA AM in the write phase. Working principles

Optical Module Electronics Working principles 5 ns 200MHz Write Freq. The Analogue Memory LIRA (256 cells x 3 channels) samples at 200 MHz and transfers the samples at 10 MHz. The 200 MHz clock is produced by PLL starting from 20 MHz Master Clock. Each LIRA samples during write phase: Anode signal; Dynode signal; 20 MHz Master clock. The number of samples is 10 SPE and 100 NSPE (*); Two voltage levels Va e Vb allows offset calibration (*) The 2 LIRA AM are alternatively in write and read phase. When START signal arrives (Control Unit): One of the LIRA start sampling (10) and if no NSPE signal arrives from TSPC starts reading else continues sampling (100) and then starts reading; The second LIRA waits and only if the first LIRA is reading starts its writing phase; (*) Remotely settable by Slow Control 2 Control Unit supervises the working state of the 2 LIRA. If a LIRA ends its writing phase and the other is still reading one have dead time.

Optical Module Electronics Working principles 100 ns 010..011 A 16 bit counter counts Master Clock cycles. A FIFO stores data coming from the counter. In the read phase LIRA transfer a suitable number of samples (anode o dynode) to a 10 bit 10 MHz commercial ADC. The sampled Master Clock, Hi or Low, is stored in a suitable logic to give fine informations relative to the arrival time of the signal respect to the Master Clock. Once a LIRA has been read and data have been converted by the ADC, the last is put by Control Unit in the Power Down state. In few Clock cycles, anyway, ADC is ready to convert again. Data flow going to the Concentrator is administrated by Control Unit through Data Packing and Transfer Unit. Data are realligned, labelled, compressed and packed. Encoding ADC 10 bit 10 MHz 3 The first LIRA completed the read phase and waits a new trigger. The other one now is ready to be read.

LIRA03 LIRA04 LIRA05 AMS 0,35 mm CMOS Technology Europractice MPW

LIRA05 CHIP AMX2 200 MHz Write 10 MHz Read Mixed Digital Analogue LIRA’s PLL Shielded PLL Stand Alone 200 MHz Slave Clock Generator T&SPC Substrate decoupling Mixed Digital Analogue Mixed Digital Analogue Pure Analogue AMX2 200 MHz Write 10 MHz Read LIRA05 CHIP

Test Results LIRA05 - PLL PLL stand alone Jitter = 1.2711e-010 s State Analyzer 4GHz Master Clock 20 MHz PLL out 200MHz Jitter = 1.2711e-010 s

Trigger & Single Photon Classifier

T&SPC: Slow Control Interface V ref Thr eshold 1 2 Too High Start NSPE Dyn M ore han O ne H it Too Long 5 bit DAC Shift Register Code Enable Clock Reset input 5 bit DAC Shift Register Code Enable Clock Reset V input 5 bit DAC Shift Register Code Enable Clock Reset V input T & SPC V ref Thr eshold 1 2 Too High Start NSPE Dyn M ore han O ne H it Too Long 5 bit DAC Shift Register Code Enable Clock Reset input Too Too High High V V ref ref Start Start Slow Slow T T & & SPC SPC NSPE NSPE Control Control Thr Thr eshold eshold 1 1 Dyn Dyn Serial Serial Thr Thr eshold eshold 2 2 M M ore ore T T han han O O ne ne H H it it Code Code Too Long Too Long And And Control Control Digital Data Digital Data Analogue Data

LIRA05

Test Setup Dedicated Software DAQ (LabView) Test Board

DC Characterization LIRA05 [V] Single Cell = 50 samples DC input Sample (2ns) Vin 0 ÷ 3,3 Volt 256 cells channel 1 AM 1 Write-Read cycle 500Msample/sec DAQ Board

DC Characterization LIRA05 Cell value= mean of corrisponding 50 sample [V] Cell

Calibration Results: cell gain and offset Gain > 1 (not uniform) Offset < 100 mV (not uniform)

AC Characterization Lira05 10 MHz 1 Vpp Sinusoid Blue =Sampled sinewave Red = Calibrated sinewave Cell Cell [V] It’s possible to calibrate the AM cell by cell Cell

Deviation from linearity distribution Vin [V*10] Vin [V*10] 3.5 mV rms resolution over all input dynamic : 1,5 V = 8-9 bit Not uniform Pedestal at input voltage variation

LIRA05 AC Characterization

Control Unit (CU) and Slow Control The CU is dedicated to the supervision of the whole operation of the OM electronics. It also receives and opportunely rebroadcasts the signals for the slow control. Actually the CU has been realized by the Bologna collaborators in a Field Programmable Gate Array (FPGA) XILINX XC4085-1PG559. It has been successfully tested together with the T&SPC and LIRA AMs.

Test LIRA05 chip CU FPGA Bologna

Considerations on chip LIRA05 and FPGA Bo New version needed Not Uniform Gain e Offset over all channels -> CALIBRATION Input Bandwidth ~ 20 MHz (insufficient) T&SPC tested ok PLL 200 MHz tested ok PLL 400 MHz -> new routing Slow Control Interface tested ok Power Dissipation of the whole chip < 200 mW FPGA Interfacing tested ok Possible OM Test -> new Board

New LIRA06 Chip Analog Memory (2 units in buffer mode) T&SPC New cell addressing timing (sampling period > 1 clock cycle) 64 cells 1 channel AM x 2 Bigger Sampling Capacity (2pF) New Readout system (Lower Power Consumption) 200 MHz Internal Control Unit a 200 MHz directly connected to new T&SPC Fine Time stamp -> on chip 4 bit counter T&SPC PMT Signal classification -> about 10 ns 2 bit anode/dynode 3 bit SPE/NSPE – double shot – Time Window Input Analog Multiplexer control PMT supply voltage control by Slow Control New Slow Control Interface -> 30 bit Input Analog Multiplexer Controlled by new T&SPC Output Analog Multiplexer Only one 10 bit Flash ADC needed Input Antialiasing 90 MHZ LPF 200 MHz PLL (LIRA05) 400 MHz PLL selectable for sampling

Comparator Thresholds and Time Window used for Classification Out1 64cellx1ch SCA PMT AMUX 10 bit 10 MHz ADC 10 bit 10ns delay Sampling Clk Working in Buffer Mode LPF 50W Anode Dinode I1 I2 Out1 SCA CTRL Signals Out1 IN AMUX 64cellx1ch SCA Sampling Clk Anode 2 bit selection code SCA CTRL Signals Out Time Stamp 200 MHZ PLL Control Unit PMT Vctrl 4 lines T&SPC Classif. code Counter In 20 MHz Master Clock 20 bit Serial Code Slow Ctrl Interface Comparator Thresholds and Time Window used for Classification Out VLSI Chip 400 MHZ PLL Commercial Device In