An Introduction to Silego's High Voltage Integrated Power Switches March 2017 v.1.0

Silego HFET Integrated Power Switch Advantages Proprietary CuFET™ Technology Ultra low RDSON nFETs: Single as low as 13.3 mΩ; Back-to-back (B2B), Reverse-current Block (RCB) as low as 50 mΩ Ultra-small package sizes: < 5 mm2 STQFNs, 0.4 mm pitch Continuous operating currents: up to 6 A Greater flexibility in power sequencing Adjustable VOUT eliminates “RC” tuning variation → controlled inrush current Faster overall power-up sequencing Multiple Built-in System-level protection circuits Input under/over-voltage protection Fixed or resistor-adjustable current limit Short-circuit protection Thermal shutdown with auto restart Automatic nFET SOA protection Reverse-current blocking Logic-level Turn-on Signaling Eliminates external level shift or charge pump circuitry to drive FET Open-drain FAULT  Signaling (Selected part numbers) Open-drain Power Good Signaling (Selected part numbers) Analog Current Monitor Output (Selected part numbers) UL Certification (Selected part numbers)

Silego’s Integrated CuFET™ MOSFET Technology Single-die Integration: Cu-FET™ Technology → Inverted-die packaging → Eliminates bond wires & lead frame 0.18-µm Control Circuitry + High-IDS/Low RDSON n-channel MOSFETs Foundry Process: Low-voltage IPSs → 3.6V or 5V CMOS Logic 24V High-voltage IPSs → 5V CMOS Logic + High-voltage Add-on Module Low sheet ρ interconnects Drain Source Top-side Redistribution Layer Octagonal FET “Cell” Control Circuit Gate Metal Layers & Vias FET Array Gate Channel Channel Optimal Range: 1A ≤ IDS ≤ 10A 20mΩ RDSON ~100,000 FET “cells” Note: Not to scale

Silego’s Integrated CuFET™ MOSFET Technology (for Flip Chip) TDFN Lead Frame Low sheet ρ Cu pillars 0.55mm Plastic package encapsulant Note: Not to scale

Typical Block Diagram of HFET1 IPSs Capacitor for adjusting VOUT slew rate and inrush current control Proprietary CuFET™ technology for very low RDSON Downstream Load Details: FPGA or application processor LCD Display BT Radio or WLAN USB or Powered ports Buck/Boost converter or LDO HV fan motor (inductive load) Resistor for adjusting Active Current Limit threshold 1.6 x 3.0 x 0.55 mm 18 pin

HFET1 Over-current Protection If current-limit condition is triggered, then thermal protection is activated. IPS operates in current limit… Thermal protection remains activated indefinitely until overload is disabled. When current-limit protection is is triggered, …until Thermal Shutdown is activated; TJ > TSD … FAULT is asserted

HFET1 SOA Protection If, during ACL operation, package power dissipation exceeds 5W or 15W(*), SOA protection is activated. IPS remains in current limit while PD remains< 5W or 15W …the IPS’s 5W or 15W SOA threshold is triggered. When current-limit protection is triggered… … FAULT is asserted. SOA protection cycles IPS ON-OFF indefinitely until overload is disabled. * Depends on the part number

High-power IPSs without Internal SOA Protection

Silego’s HFET1 SOA Protection

HFET1 5W SOA Protection on Start-up VIN = 20 V, CLOAD = 10 µF, RLOAD = 10 , RSET = 30.1 k, Initial Start-up Condition Since FET PD at Start-up > 5W or 15W, SOA protection is activated. SOA protection cycles IPS ON-OFF-ON indefinitely until IPS is turned OFF.

Silego’s HFET1 Linear/Monotonic VOUT Ramp Profile Typical Turn ON operation waveform for VIN = 20 V, CSLEW = 10 nF, CLOAD = 10 µF, RLOAD = 100 

Learn more about Silego’s HFET1 products at our website http://www.silego.com/products/hfet1.html    GreenFET3 Product Selector Guide (English) HFET1 Product Selector Guide AN-1068 GreenFET3 Integrated Power Switch Basics