LLRF for ESS: Requirements and System design Anders J Johansson

LLR group organisation, two views ESS Accelerator Division RF Group LLRF ESS Accelerator Tech. Board Coll. Board Lund University LTH Electrical and Information tech. Control department

LLRF Group Associate Prof. Radio Systems Anders J Johansson, EIT M.Sc. Anders Svensson, 100%, EIT Prof. Bo Bernhardsson, 20%, Automatic Control Ph.D. Fredrik Kristensen, 100%, EIT Associate Prof. Markus Törmänen, 20%, EIT M.Sc. Olof Troeng, 60%, Automatic Control Rihua Zeng, ESS

Work mode Group situated at LU campus, 10 min. walk from ESS offices. Participates in bi-weekly ESS RF group meetings and regular Accelerator Division meetings, as well as daily activities. Are in close contact with ESS collaborators. Are in contact with and have visited other labs to get input from their experience (DESY, SNS, J-Parc, SLAC, CERN, PSI, MAX-IV).

Outside LLRF Group is involved in additional areas such as Master Oscillator, Freq. Reference line, Hardware Harmonization, Test stands, etc. Other people and groups at Lund University are involved in additional areas.

LLRF at ESS Controls the phase and amplitude of the field in the cavities to within x degree / y %. Starts at cavity field pickup connector on cavity/cryomodule. Ends at input to the pre-amplifier. Controls the fast piezo tuners. Controls the slow stepper motor tuners.

Performance requirements The following are the requirements of the cavity field with reference to the beam phase. Cavity Phase stability (RMS for one pulse) Amplitude stability (RMS for one pulse) Phase excursion (Peak, first 10 us) Amplitude excursion (Peak, first 10 us) RFQ 0.2 deg. 0.2 % 1.0 deg. 1.0 % Buncher DTL Spoke 0.1 deg. 0.1 % 0.5 deg. 0.5 % Medium Beta High Beta Drift: Adjacent cavities max. +/- 0.1 deg. Any two cavities within 100 meter max. +/- 1 deg.

Interface requirements These are being worked out, most are in close-to ready state. In general: The interface to the cavity is at the connector on the cavity/cryomodule surface in the tunnel. The interface to the phase reference line is at a connector to the tap of the line in the tunnel.

Timing and Phase Reference MRF timing system in gallery distributes triggers. Phase reference line in tunnel.

LLRF system : General view

Cavities Cavity Freq. (MHz) Units Temp. Tuning Comment RFQ 352.21 1 Warm Water 20 add. field probes, 2 power couplers Buncher 3 Motor DTL 5 8 add. field probes 2 power couplers / cav. Spoke 26 Cold Motor Piezo Medium-Beta 704.42 36 High- Beta 84

RF systems overview Cavity Freq. (MHz) Units Power Tech. Comment RFQ 352.21 1 2.8 MW Klystron 2 power couplers Buncher 3 30 kW Solid-state DTL 5 2 power couplers / cav. Spoke 26 400 kW Tetrode Dual 200 kW tetrodes Medium-Beta 704.42 36 1.5 MW High- Beta 84 1.2 MW IOT Multibeam IOT in development.

Design concept Digital implementation of fast control in FPGA Move complexity from firmware to software Modular design for simple maintenace Modular design for large volume procurement Partly redundant design for availability Integrated into EPICS for control IPMI (Intelligent Platform Management Infrastructure) for simple, and preventive, maintenance

High level LLRF architecture Procedures Schemes that involves longer times and multiple pulses. Algorithms Updates that takes place between pulses (68 ms). Functions Real-time control within a pulse (3.5 ms). Procedures Scripts CPU EPICS Algorithms Software CPU PCIe LLRF Functions Firmware FPGA

PI-control Classic controller Proportional Integral Two independent, but equal, PI-controllers, on I and Q. An additional inner loop for linearization is planned.

FeedForward control Based on stationarity of system Every pulse looks the same Adaptation handles slow drift

Linearization Other possibility is an inner PI-loop, as described. Picture: Agilent Other possibility is an inner PI-loop, as described.

Mechanical and electrical design Chassis and crates in 19” racks Termally controlled environment System build on MTCA.4 crates See separate presentation Grounding All incoming cables to the LLRF system is grounded in a common plate at the top of the cabinet.

352.21 MHz MTCA.4 Warm Linac Timing Interlock Fan Tray x 2 PSU x 2 CB control on backplane Timing triggers MCH supervision External I/O Ethernet on backplane CPU LO-generation Phase reference Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Timing LO/REF Timing RF/VM 352 MHz FPGA/ADC Interlock Modulator voltage Beam current Vectormodulator out MCH Fan Tray x 2 EPICS, Supervision PSU x 2 230 V AC

352.21 MHz MTCA.4 Warm Linac, more inputs CB control on backplane Timing triggers MCH supervision External I/O Ethernet on backplane CPU LO-generation Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Timing LO/REF Timing RF/VM 352 MHz FPGA/ADC Interlock Modulator voltage Beam current Vectormodulator out FPGA/ADC RF/(VM) X Y Z MCH Fan Tray x 2 EPICS, Supervision PSU x 2 230 V AC

352.21 MHz MTCA.4 Spoke Timing Interlock Fan Tray x 2 PSU x 2 230 V AC CB control on backplane Timing triggers MCH supervision External I/O Ethernet on backplane CPU LO-generation Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Timing LO/REF Timing RF/VM 352 MHz FPGA/ADC Interlock Modulator voltage Spare Vectormodulator out FPGA PZ Piezo 1 Piezo 2 Monitor MCH Fan Tray x 2 EPICS, Supervision PSU x 2 230 V AC

704.42 MHz MTCA.4 Elliptical Timing Interlock Fan Tray x 2 PSU x 2 CB control on backplane Timing triggers MCH supervision External I/O Ethernet on backplane CPU LO-generation Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Phase referense Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Timing LO/REF Timing RF/VM 704 MHz FPGA/ADC Interlock Modulator voltage Spare Vectormodulator out FPGA PZ Piezo 1 Piezo 2 Monitor MCH Fan Tray x 2 EPICS, Supervision PSU x 2 230 V AC

Second option of LO-generation implementation CB control on backplane Timing triggers MCH supervision External I/O Ethernet on backplane CPU Phase reference Cavity Pickup VM out PreAmp Out PowerAmp out PowerAmp Refl Cavity In Cavity Refl Timing Timing RF/VM 704 MHz FPGA/ADC LO/REF Interlock Modulator voltage Spare Vectormodulator out FPGA LO-generation Phase reference MCH Fan Tray x 2 EPICS, Supervision PSU x 2 230 V AC

Three LLRF systems running today. 352 MHz LLRF test bench Lund University 352 MHz LLRF system Freia test hall Uppsala University 704 MHz LLRF test bench Lund University