2014 Spring ASIC/SOC Design A Top-down Design Methodology with Embedded Aging Sensors for Robust System Design Xinfei Guo 5/9/2014

Outline Motivation Aging sensor cell Top-down design methodology Future work

Aging/Wearout Reliability: time dependent degradation Device level: parametric shift over time (e.g.Vth,u) Circuit and architecture level Irreversible and reversible(e.g. BTI) [M. Alam et al. Microelectronics Reliability ’07] Transistor Aging/wearout is one of the most important reliability issues of CMOS circuit. It is a long term process that is caused by several combined physical mechanisms. In device level, it shows the impact of the parametric shift, like threshold voltage. In circuit and above abstractions, it leads to either timing error, failure, high power, and so on. Also to conquer this, design margin is further increased. Also it becomes more and more significant with advanced technology node. Aging consists of both reversible and irreversible phenomena which accumulate at different rates under stress, e.g. voltage stress. In this paper, we are focusing on reversible stress, especially BTI, which is biased temperature instability since it is the most dominant aging mechanisms that shifts the threshold voltages with time. NBTI for example, when PMOS is under stress, it is the stress phase and when the voltage is removed, it has some levels of recovery, but usually at a very slow rate. For PBTI it is the same for NMOS.

Bias Temperature Instability(BTI) Trapping/Detrapping [J. Velamala et al. DAC’12] Get worse and worse Both NBTI and PBTI Stress and Recovery [M. Lee et al. ASP-DAC ’11] Hole trapping is generally modeled by considering tunneling of channel carriers into oxide defects. These oxide defects can either be pre-existing [15, 18] or generated by electrical stress. According to the latest trapping detrapping theory, the threshold voltage of the transistor increases when a trap captures a charge carrier in the stress phase. If the transistor is in recovery phase, some of the interface traps can be annealed, and the number of occupied traps reaches a new equilibrium and results in partial recovery. According to the trapping theory, threshold voltage of a device increases when a trap captures a charge carrier, resulting in reduction of drain current. If the device is not under stress, only localized traps with energy close to Fermi level can change their states, originating into low frequency noise.

Why Aging Sensor? Track and monitor aging Adaptive circuit tuning (e.g. DVFS) “Check engine light” for recovery techniques

Related Work Ring Oscillator based “Silicon Odometer” [T. Kim et al. VLSI ’07, JSSC ’08] - Area overhead, complex, process variation Metastable element based [A. Cabe et al. ISQED ’09][S. Wooters, et al. TVLSI ’12] - Small and embedded - Good time resolution - Distributed The sensor in Kim et al. [16] is comprised of two 105-stage ring oscillators, and Karl et al. [17] deploys a 15-stage NAND ring oscillator biased in subthreshold mode. , attaining good accuracy while sacrificing area and complexity

Sensor Cell Set the margin Design the sensor Check the engine a typical bathtub curve, plotting failure rate versus chip age. The aforementioned sensors can provide NBTI degradation data for any point in time, which can require a high degree of sensor characterization, calibration, and modeling the goal of this work is to identify one or more critical points along the way and consider them to be the end of life affected by a percentage of degradation. In essence, our sensors serve as a chip “check engine light,” Initially, a current slightly larger than the reference inverter, where the percentage margin is equivalent to as discussed. This margin is simply set by up-sizing the degradation tracking inverter’s pMOS device. Normally the sensor is in tracking mode. This modality sets the reference input to VDD, turning off its pMOS, and the degradation input is set by the designer to track a particular switching activity . After a set period, the sensor can cease tracking and measure current degradation. This is done by setting the reference-in and degradation-in buffer to output high Z. is set high, pulling down the inputs of both inverters, turning on both inverters’ pMOS. Another control signal turns off and closes the switches set by . This creates a fight condition where both inverters try to set each input high. Because the tracking inverter is larger, it will win the fight until the current through has degraded to a point lower than the reference. Once the reference is stronger than the “check engine light” is triggered and a warning can be sent to the user. The close spatial locality of the reference and sensor inverters heavily reduces the impact of systematic intra-die variations. Also size the PMOS larger. Source: S. Wooters, et al. TVLSI ’12

Why Top-Down Design? Top-down design for sensor itself - Reduce design time - Reduce impact of process variations - Designware cell Top-down design with sensor embedded - Different behavior of each block - Different Thermal Behavior - Distributed with Smaller area overhead

Sensor Cell Instantiate the library cell

Scan chain cell – Read Output New Scan Cell Scan cell

Scan chain cell

New ScanCell Flow agingsensor.v Design Compiler agingsensor_dc.v newscancell.v newscancell_dc.v IC Compiler agingsensor.CEL agingsensor.FRAM newscancell.CEL newscancell.FRAM Std cell lib

Top-down design with aging sensor embedded Architectural choices, RTL compilation and simulation (VCS) Logic synthesis (Design Compiler) Formal verification (Formality) Generation of test patterns (TetraMAX) Physical design (IC Compiler) Physical Verification (Hercules) Layout Parasitics Extraction (StarRC) SPICE-level simulation of completed design (HSPICE) Basic DC Synthesis(Design Compiler) Basic Scan Synthesis Flow (Design For Test Compiler) Update the netlist Add to Reference Library (New scan cell library)

Case Study: Johnson Counter … n=total # of SDFF; t=user defined parameter; # application dependent for(i=0;i<=n;i+t) {Replace the SDFFARX1 with sensorSDFFX1; Add global control signals; D=deg_in; }

Case Study: Johnson Counter

Case Study: Johnson Counter

Future work Verification Tradeoff between # of sensor vs. accuracy Placement of the sensor Both NBTI and PBTI Optimize area Trigger recovery Silicon Validation

Thanks! Q & A