Microprocessor and Assembly Language Lecture-3-The 80x86 Microprocessor Muhammad Hafeez Department of Computer Science GC University Lahore

Today’s Agenda History of Computer Intel Microprocessors

History of Computers Zeroth Generation (1642-1945) - Mechanical Blaise Pascal – Four Function Calculator Charles Babbage – Difference Engine and Analytical Engine First Generation (1945-1955) – Vacuum Tubes ENIAC (Electronic Numerical Integrator and Computer) – 30 Tons, 1800 vacuum tubes, 1400 KW power EDVAC (Electronic Discrete Variable Automatic Computer IBM 701 – IBM first industrial machine

History of Computers 2nd Generation (1655-1965) - Transistors DEC – PDP-8 12 Bit Accumulator, 32K 12 bit word 3rd Generation (1965-1980) – Integrated Circuits IBM Systems/ 360 DEC – PDP-11, 128K Memory 4th Generation (1980-todate) – Very Large Scale Integrated Circuits Microprocessors

History of Computers 2nd Generation (1655-1965) - Transistors DEC – PDP-8 12 Bit Accumulator, 32K 12 bit word 3rd Generation (1965-1980) – Integrated Circuits IBM Systems/ 360 DEC – PDP-11, 128K Memory 4th Generation (1980-todate) – Very Large Scale Integrated Circuits Microprocessors

Intel Microprocessors Intel 8086/8088 (CISC) Intel 80286 – IBM AT Intel Architecture – 32 (IA-32) Family Intel386 Intel486 Pentium (RISC) Pentium Pro Intel 64-bit Processors Intel64 IA-32e

Intel 4004 A bit slice 4-bit Microprocessor (1971) Addressable Memory 640 Bytes 45 Instructions Operator at high speed, lacked improvement in word size Use BCD code

Intel 8008 A 8-bit Microprocessor (1972) Addressable Memory 16KB 48 Instructions Addition took 20s

Intel 8080 A 8-bit Microprocessor (1974) 8-bit data bus, 16-bit address bus Addressable Memory 64K CP/M Operating System Addition took 2.0s

Intel 8086/8088 IBM-PC Used 8088 (1978) 8088 open system (h/w, s/w documents open) 2.5 millions of instructions per second 1 MB addressable RAM 16-bit registers 4- or 6-byte instruction cache 16-bit data bus (8-bit for 8088) contained 246 instructions (20,000 variations) separate floating-point unit (8087) Our Target Processor

Intel 80286 IBM-AT 16 Bit Data Bus 24 Bit Address bus Protected Memory Feature 8.0 MHz, 4.0 MIPS, several time faster than 8086

Intel Architecture-32- IA-32 Family 4 GB addressable RAM, 32-bit registers, memory management unit paging (virtual memory) Intel486 50 MHz, 50 MIPS instruction pipelining 8-16KB cache Pentium (RISC) 60 MHz, 110 MIPS contains two independent internal integer processors called superscaler technology executes two instructions not dependent on each other, simultaneously per clocking period 32-bit address bus, 64-bit internal data path

Intel Pentium Pro A recent entry, formerly named the P6. 21 million transistors, integer units, floating-point unit, Clock frequency 150 and 166 MHz Internal 16K level-one (L1) cache. 8K data, 8K for instructions 256K level-two (L2) cache Three execution engines, to execute up to three instructions at a time. Address 4G-byte or a 64G-byte memory system. 36-bit address bus if configured for a 64G memory system

Intel 64 Bit Processors Intel64 64-bit linear address space Intel: Pentium Extreme, Xeon, Celeron D, Pentium D, Core 2 and Core i7 IA-32e Mode Compatibility mode for legacy 16- and 32-bit applications 64-bit Mode uses 64-bit addresses and operands

CISC and RISC CISC complex instruction set large instruction set high-level operations requires microcode interpreter examples: Intel 80x86 family RISC reduced instruction set simple, atomic instructions small instruction set directly executed by hardware examples: ARM (Advanced RISC Machines) DEC Alpha (now Compaq)

Intel Memory Structure TPA (Transient Program Area) System Area XMS (Extended Memory System)

Intel Memory Structure

Intel Memory Structure First 1M byte of memory often called the real or conventional memory system. Intel microprocessors designed to function in this area using real mode operation 80286 through the Core2 contain the TPA (640K bytes) and system area (384K bytes). Extended memory up to 15M bytes in the 80286 80386 I 4095M bytes in 80486 80386DX, Pentium microprocessors. The Pentium Pro through Core2 computer systems have up to 1M less than 4G or 1 M less than 64G of extended memory.

TPA

TPA Holds DOS and other programs that control the system TPA is a DOS concept and not applicable to windows Also stored currently active/inactive DOS application programs Size = 640K

TPA Interrupt vectors access DOS, BIOS (basic I/O system), and applications. Areas contain transient data to access I/O devices and internal features of the system. these are stored in the TPA so they can be changed as DOS operates The IO.SYS loads into the TPA from the disk whenever an MSDOS system is started. IO.SYS contains programs that allow DOS to use keyboard, video display, printer, and other I/O devices often found in computers. The IO.SYS program links DOS to the programs stored on the system BIOS ROM. Drivers programs that control installable I/O devices DOS drivers normally have an extension of .SYS COMMAND.COM (command processor) controls operation of the computer from the keyboard when it operates under DOS

System Area

System Area Smaller than the TPA; just as important. The system area contains programs on read-only (ROM) or flash memory, and areas of read/write (RAM) memory for data storage. First area of system space contains video display RAM and video control programs on ROM or flash memory. area starts at location A0000H and extends to C7FFFH size/amount of memory depends on type of video display adapter attached

Windows Memory Difference between DOS TPA First 2 GB Size/ Location TPA First 2 GB System Area is Last 2 GB

Internal Structure of 8086 Two ways to make processor fast Increase working frequency Demands Technology, No. of IC’s in a Package with Respect to Cost and Technology Change Internal Working Pipelining Fetch and Execute at the same time

Pipelining in 8086 To Implement the idea of pipelining split processor into Execution Unit (EU) Execute Instructions Bus Interface Unit (BIU) Access Memory and Peripherals Keeps ahead of EU by keeping a buffer for pre-fetched instructions usually 6 byte Pre-fetch instruction when buffer has 2 byte space In a jump condition buffer is flushed out, it is called jump penality

Internal Structure of 8086

Programming Model of Intel Registers:

General Purpose Registers RAX (64-Bit), EAX (32-Bit), AX (16-Bit), AH (8-Bit), AL (8-Bit) Also called Accumulator, used implicitly as an operand in some instructions like division and multiplication, also generate shortest machine code RBX (64-Bit), EBX (32-Bit), BX (16-Bit), BH (8-Bit), AL (8-Bit) Hold based index, offset address of memory in all versions of Microprocessors RCX (64-Bit), ECX (32-Bit), CX (16-Bit), CH (8-Bit), CL (8-Bit) Serves as loop counter, also used in shift and rotate instructions

General Purpose Registers RDX (64-Bit), EDX (32-Bit), DX (16-Bit), DH (8-Bit), DL (8-Bit) Hold data for multiplication and division instructions, also used in I/O operations AX, BX, CX, DX and their High / Low parts are used in 8086

Segment Registers to Address Segmented Memory A Typical assembly language program has four segments in memory Code Segment Data Segment Stack Segment Extra Segment

Segmented Memory 8085 predecessor of 8086 had 64K addressable memory, 216 memory locations, 16 address lines 8086 has 1MB addressable memory, 220 memory locations, 20 address lines For compatibility reason memory in 8086 is segmented in 64K segments, each assigned to Code Segment, Data Segment, Stack Segment and Extra Segment Therefore, a program in 8086 can handle at maximum of 64K Stack Segment, 64K Data Segment, 64K Code Segment and 64K Extra Segment. Segment starts at every 10H=16 bytes, called paragraph, an address divisible by 16 called a paragraph boundary

Logical Addresses and Physical Addresses Three types of addresses Physical Address Logical Address Offset Address Physical Address: A 20-bit address to address 1MB memory Range from 00000H to FFFFFH Offset Address: A 16-bit address to address 64KB memory Range from 0000H to FFFFH Used to address memory within 64K segment

Code Segment Logical Address for Code Segment: Consist of Logical Address using IP Register as Offset referred to as CS:IP Physical Address of Code segment: CS shifted 1 Hex and add IP, result is 20-bit address Physical Address Calculation Example: CS = 2500H, IP= 95F3H Logical Address CS:IP, 2500:95F3 Physical Address 25000H 95F3H 2E5F3H (Physical 20-bit address)

Data Segment Assume, use memory to Add 5 bytes of data, 25H, 15H, 05H, 25H, 15H To take each byte for addition, each time data is referred The need to set aside an area for data segment arose Just like CS:IP for code segment, Data Segment has an offset stored in register Example: DS:0200 = 25H DS:0201= 15H DS:0202= 05H DS:0203=25H DS:0204=15H

Data Segment It is more convenient to store offset address of data segment in register In 8086 BX, SI and DI are used as offset register for data segment

Stack Segment Used to hold the values stored in Stack during program execution

Extra Segment This segment is used if the program spans beyond 64K for Code or Data Segment, i.e. we have to use two segments for a program

Pointers and Index Registers Pointers and Index Registers points to memory location (offset address) Can be used in arithmetic and other operations Stack Pointer (SP): Used in conjunction with Stack Segment (SS) to point to Stack area in memory Base Pointer (BP): Primarily used with Stack Segment (SS) to access area of stack, however, can be used to access other areas of memory with other segments Source Index (SI): SI is used to access memory area in Data Segment (DS), increment SI to access consecutive memory locations

Pointers and Index Registers Destination Index (DI): Work same way as SI, string instructions use DI Instruction Pointer (IP): Registers covered so far, are for data access, IP access Instructions in the memory in conjunction with Code Segment (CS), each time an instruction is executed IP is incremented and points to next instruction. IP cant be managed in the program.

Segments and Their Offset Registers -Summary- Segment Register Offset Register CS IP SS SP, BP DS BX, SI, DI ES Any Register Except SP and IP

Memory (Non-Overlapping Segments

One Physical Address-Many Logical Addresses Physical Address starts at 15020H Possible Segment:Offset Pair to point at this address Shows Dynamic behavior of Segment:Offset addressing

Segment Wrap-Around Consider a Physical address FF590H and Wrap Around (FF590H+FFFFH)

Memory Overlapping Segments

Memory Overlapping Segments

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