Section 9: Virtual Memory (VM) Overview and motivation Indirection VM as a tool for caching Memory management/protection and address translation Virtual memory example Address Translation

VM for Managing Multiple Processes Key abstraction: each process has its own virtual address space It can view memory as a simple linear array With virtual memory, this simple linear virtual address space need not be contiguous in physical memory Process needs to store data in another VP? Just map it to any PP! Address translation Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 ... N-1 (e.g., read-only library code) PP 6 Virtual Address Space for Process 2: PP 8 VP 1 VP 2 ... ... N-1 Address Translation M-1

VM for Protection and Sharing The mapping of VPs to PPs provides a simple mechanism for protecting memory and for sharing memory btw. processes Sharing: just map virtual pages in separate address spaces to the same physical page (here: PP 6) Protection: process simply can’t access physical pages it doesn’t have a mapping for (here: Process 2 can’t access PP 2) Address translation Virtual Address Space for Process 1: Physical Address Space (DRAM) VP 1 VP 2 PP 2 ... N-1 (e.g., read-only library code) PP 6 Virtual Address Space for Process 2: PP 8 VP 1 VP 2 ... ... N-1 Address Translation M-1

Memory Protection Within a Single Process Extend PTEs with permission bits MMU checks these permission bits on every memory access If violated, raises exception and OS sends SIGSEGV signal to process Physical Address Space Process i: Valid SUP WRITE EXEC Address VP 0: VP 1: VP 2: Yes Yes No No PP 6 No No Yes PP 4 PP 2 Yes Yes No PP 2 • PP 4 PP 6 Process j: Valid SUP WRITE EXEC Address PP 8 No Yes No PP 9 PP 9 Yes No No PP 6 No Yes No PP 11 PP 11 Address Translation

Address Translation: Page Hit 2 CPU Chip Cache/ Memory PTEA MMU 1 PTE CPU VA 3 PA 4 Data 5 1) Processor sends virtual address to MMU (memory management unit) 2-3) MMU fetches PTE from page table in cache/memory 4) MMU sends physical address to cache/memory 5) Cache/memory sends data word to processor Address Translation

Address Translation: Page Fault Exception Page fault handler 4 2 CPU Chip Cache/ Memory Disk PTEA Victim page MMU 1 5 CPU VA PTE 7 3 New page 6 1) Processor sends virtual address to MMU 2-3) MMU fetches PTE from page table in cache/memory 4) Valid bit is zero, so MMU triggers page fault exception 5) Handler identifies victim (and, if dirty, pages it out to disk) 6) Handler pages in new page and updates PTE in memory 7) Handler returns to original process, restarting faulting instruction Address Translation

Hmm… Translation Sounds Slow! The MMU accesses memory twice: once to first get the PTE for translation, and then again for the actual memory request from the CPU The PTEs may be cached in L1 like any other memory word But they may be evicted by other data references And a hit in the L1 cache still requires 1-3 cycles What can we do to make this faster? Address Translation

Speeding up Translation with a TLB Solution: add another cache! Translation Lookaside Buffer (TLB): Small hardware cache in MMU Maps virtual page numbers to physical page numbers Contains complete page table entries for small number of pages Modern Intel processors: 128 or 256 entries in TLB “x86info -c” on Intel Core2 Duo CPU: L1 Data TLB: 4KB pages, 4-way set associative, 16 entries Data TLB: 4K pages, 4-way associative, 256 entries. L1 Data TLB: 4MB pages, 4-way set associative, 16 entries Data TLB: 4MB pages, 4-way associative, 32 entries Address Translation

TLB Hit A TLB hit eliminates a memory access CPU Chip TLB Cache/ MMU 2 PTE VPN 3 Cache/ Memory MMU 1 CPU VA PA 4 Data 5 A TLB hit eliminates a memory access Address Translation

TLB Miss CPU Chip TLB 4 2 PTE VPN Cache/ Memory MMU 1 3 CPU VA PTEA PA 5 Data 6 A TLB miss incurs an additional memory access (the PTE) Fortunately, TLB misses are rare Address Translation