ENG2410 Digital Design “Combinational Logic Design” Fall 2017 S. Areibi School of Engineering University of Guelph

Resources Chapter #4, Mano Sections 4.1 Combinational Circuits 4.3 Decoding 4.4 Encoding 4.5 Multiplexers 4.6 Comb Function Implementations School of Engineering

Week #4 Topics Decoders Encoders Multiplexers Demultiplexers Combinational circuit Implementation Encoders Priority Encoders Multiplexers Combinational Circuit Implementation Demultiplexers School of Engineering

Devices on a Bus Enable Device #0 Control Unit Disable Device #1 I have 4 devices to put info on a Bus I must have only one device active at a time! I will need 4 wires from my Control Unit If I need to communicate with more devices then I will need many wires!! Control Unit Enable Device #0 Disable Device #1 Disable Device #2 Disable Device #3 BUS

Address Decoding Device #0 Control Unit Device #1 Device #2 Device #3 I have 4 devices to put info on a Bus I must have only one device active at a time! But! I can afford to have only 2 wires from my control unit Control Unit Device #0 1 Device #1 Device #2 Device #3 BUS

Decoders Are circuits with n inputs and 2n outputs Drives high the output corresponding to binary code of input Several Applications: Address Decoding, … D0 A D1

2-to-4 Line Decoder Notice they are minterms

Other Decoders Examples: 3-to-8 Decoder 4-to-16 Decoder 3-to-8 Line Binary to Octal, Binary to Hex, e.t.c 3-to-8 Line Decoder 4-to-16 Line Decoder 3 8 4 16

Truth Table, 3-to-8 Decoder Example: Binary to Octal, Binary to Hex, e.t.c Notice they are minterms

3-to-8 Line Decoder Schematic

2-to-4 with Enable Why use an Enable?

Enable Used for Expansion 1 1 1 1 1 1 1 1 1 1 1 1 1

Usage for Decoders Binary to Octal/Hex converters. Selecting memory banks, for example 4 memory banks can be selected individually using 2 address lines. Implementing logic circuits! Decoders are used in Micro Computer Interfacing for Keyboard and Display applications.

1. Address Decoding Memory Bank #1 CPU Memory Bank #2 Memory Bank #3

2. Decoders as General-purpose Logic n:2n decoder implements any function of n variables With the variables used as control inputs Enable inputs tied to 1 and Appropriate minterms summed to form the function Decoder generates appropriate minterm based on control signals (it "decodes" control signals) School of Engineering

Decoders as General-purpose Logic Example: Implement the following Boolean functions S(A2,A1,A0) = SUM(m(1,2,4,7)) C(A2,A1,A0) = SUM(m(3,5,6,7)) Since there are three inputs, we need a 3-to-8 line decoder. The decoder generates the eight minterms for inputs A0,A1,A2 An OR GATE forms the logical sum minterms required. School of Engineering

Decoders as General-purpose Logic S(A2,A1,A0) = SUM(m(1,2,4,7)) S School of Engineering

Decoders as General-purpose Logic C(A2,A1,A0) = SUM(m(3,5,6,7)) C School of Engineering

Example F1 = A' B C' D + A' B' C D + A B C D A B 0 A'B'C'D' 1 A'B'C'D 2 A'B'CD' 3 A'B'CD 4 A'BC'D' 5 A'BC'D 6 A'BCD' 7 A'BCD 8 AB'C'D' 9 AB'C'D 10 AB'CD' 11 AB'CD 12 ABC'D' 13 ABC'D 14 ABCD' 15 ABCD 4:16 DEC Enable C D F1 School of Engineering

Encoder Encoder is the opposite of decoder Examples: 2n inputs (or less – maybe BCD in) n outputs Examples: Octal to binary conversion Hexadecimal to binary conversion

Octal to Binary Encoder

Design of Encoder A0 = D1 + D3 + D5 + D7

Multiplexer (or Mux) Selects one of a set of inputs to pass on to output For Every 2n inputs we need n select lines Applications: Useful for choosing from sets of data Memory or register to ALU In0 Out In1 MUX In2 In3 S0 S1

2-Input Multiplexer

4-to-1 Line Multiplexer

Quad 2-to-4 Line Mux Select one set of 4 lines

Implementing Logic 2n:1 multiplexer implements any function of n variables With the variables used as control inputs and Data inputs tied to 0 or 1 In essence, a lookup table Example: F(A,B) = m0 + m2 = A'B' + AB’ A B F 1

Muxes as General-purpose Logic 2n:1 multiplexer implements any function of n variables With the variables used as control inputs and Data inputs tied to 0 or 1 In essence, a lookup table Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC A B C F 1 1 0 1 0 0 0 1 1 0 1 2 3 4 5 6 7 S2 8:1 MUX S1 S0 F A B C School of Engineering

Muxes as General-purpose Logic 2n-1:1 mux can implement any function of n variables With n-1 variables used as control inputs and Data inputs tied to the last variable or its complement Example: F(A,B,C) = m0 + m2 + m6 + m7 = A'B'C' + A'BC' + ABC' + ABC Not Optimized Optimized C A B 0 1 2 3 4 5 6 7 1 0 1 0 0 0 1 1 S2 8:1 MUX S1 S0 A B C F 0 0 0 1 0 0 1 0 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 0 1 1 0 1 1 1 1 1 C' C' 0 1 A B S1 S0 F 0 1 2 3 4:1 MUX C' C' 0 1 F School of Engineering

Demultiplexer Takes one input out to one of 2n possible outputs

VHDL

Decoder: (VHDL  Data Flow) Example: 2-to-4 decoder D3 entity dec_2_to_4 is port ( A0, A1: in std_logic; D0, D1, D2, D3: out std_logic); end entity dec_2_to_4; A(1) D2 Interface A(0) D1 D0 architecture dataflow1 of dec_2_to_4 is Signal A0_n, A1_n: std_logic; begin A0_n <= not A0; A1_n <= not A1; D0 <= A0_n and A1_n; D1 <= A0 and A1_n; D2 <= A0_n and A1; D3 <= A0 and A1; end architecture dataflow1; A0_n A1_n Functionality School of Engineering

When Else Statement mux: Y <= D0 when S1 = ‘0’ and S0 = ‘0’ else

Decoder: Data Flow #2 Interface Functionality Example: 2-to-4 decoder entity dec_2_to_4 is port ( A : in std_logic_vector(1 downto 0); D : out std_logic_vector(3 downto 0) ); end entity dec_2_to_4; architecture dataflow2 of dec_2_to_4 is begin D <= "0001" when A = "00" else "0010" when A = "01" else "0100" when A = "10" else "1000" when A = "11" else "XXXX"; end architecture dataflow2; A(1) D(2) Interface A(0) D(1) D(0) A(1..0) D(3..0) 1 Functionality School of Engineering

Dataflow VHDL Description of 4-to-1 Multiplexer -- 4-to-1 Line Mux; Conditional Dataflow VHDL Descrip library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1 is port (S: in std_logic_vector(1 downto 0); I: in std_logic_vector(3 downto 0); Y: out std_logic; end multiplexer_4_to_1;

Cont .. Dataflow VHDL Description architecture function_table of multiplexer_4_to_1 is -- Using When Else Begin Y <= I(0) when S = “00” else I(1) when S = “01” else I(2) when S = “10” else I(3) when S = “11” else `X’; end function_table;

VHDL Design Styles VHDL Design Styles dataflow behavioral (algorithmic) structural Concurrent statements Components and interconnects Sequential statements Registers State machines Test benches Subset most suitable for synthesis

Structural VHDL Description of 2-to-4 Line Decoder

Structural VHDL Description “Entity Declaration” -- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable;

Structural VHDL Description (Signals) A1_n A0_n N0 N1 N2 N3

Structural VHDL Description (Components) architecture structural1_1 of decoder_2_to_4_w_enable is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic;

Structural VHDL Description (Connecting components) A1_n A0_n architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 declaration signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); …… end structural_1; component NOT1 port(in1: in std_logic; out1: out std_logic); end component;

Structural VHDL Description (Connecting components) architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 declaration signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1;

2-to-4 Line Decoder: Complete Design -- 2-to-4 Line Decoder; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity decoder_2_4_w_enable is port (EN, A0, A1 : in std_logic; D0, D1, D2, D3 : out std_logic); end decoder_2_to_4_w_enable; A1_n A0_n architecture structural1_1 of decoder_2_to_4_w_enable is -- component NOT1 declaration -- component NAND2 signal A0_n, A1_n, N0, N1, N2, N3: std_logic; begin g0: NOT1 port map (in1 => A0, out1 => A0_n); g1: NOT1 port map (in1 => A1, out1 => A1_n); g2: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N0); g3: AND2 port map (in1 => A0, in2 => A1_n, out1 => N1); g4: AND2 port map (in1 => A0_n, in2 => A1_n, out1 => N2); g5: AND2 port map (in1 => A0, in2 => A1, out1 => N3); g6: AND2 port map (in1 =>EN, in2 => N0, out1 => D0); g7: AND2 port map (in1 => EN, in2 => N1, out1 => D1); g8: AND2 port map (in1 => EN, in2 => N2, out1 => D2); g9: AND2 port map (in1 => EN, in2 => N3, out1 => D3); end structural_1;

End Slides

Revisiting Encoder!! Why? Only ONE input is allowed to be active at a time!

What’s the Problem? What if D3 and D6 both high? Simple OR circuit will set A to 111 This is an issue!!!! Solution?

Priority Encoder Chooses one with highest priority Largest number, usually “X” in input == 0 or 1 compact Truth Table

Unfolding the Compact Truth Table 0 0 0 1 0 0 0 0 1 0 0 1 0 0 1 1 0 1 What if all inputs are zero?

Need Another Output! A Valid Output!

Expanded Truth Table (A0) X 1 D1D0 D3D2 00 01 11 10 x 1 00 01 11 10 A0 = D3 + D2D1

Valid is OR of all inputs

Structural VHDL Description of 4-to-1 Line Multiplexer S_n(0:1) D(0:3) N(0:3)

Cont .. Structural VHDL Description of 4-to-1 Multiplexer -- 4-to-1 Line Multiplexer; structural VHDL Description library ieee; use ieee.std_logic_1164.all entity multiplexer_4_to_1_st is port (S: in std_logic_vector(0 to 1); I: in std_logic_vector(0 to 3); Y: out std_logic; end multiplexer_4_to_1_st;

Cont .. Structural VHDL Description of 4-to-1 Multiplexer architecture structural_2 of multiplexer_4_to_1_st is component NOT1 port(in1: in std_logic; out1: out std_logic); end component; component AND2 port(in1, in2: in std_logic; component OR4 port(in1, in2, in3, in4: in std_logic;

Cont .. Structural VHDL Description of 4-to-1 Multiplexer architecture structural_2 of multiplexer_4_to_1_st is -- component NOT1 AND2 OR4 declarations signal S_n : std_logic(0 to 1); signal D, N : std_logic_vector(0 to 3); begin g0: NOT1 port map (S(0), S_n(0)); g1: NOT1 port map (S(1), S_n(1)); g2: AND2 port map (S_n(1), S_n(0), D(0)); g3: AND2 port map (S_n(1),S(0), D(1)); g4: AND2 port map (S(1),S(0), D(3)); g5: AND2 port map (S(1), S(0), D(3)); g6: AND2 port map (D(0), I(0), N(0)); g7: AND2 port map (D(1),I(1), N(1)); g8: AND2 port map (D(2),I(2),N(2)); g9: AND2 port map (D(3),I(3), N(3)); g10: OR4 port map (N(0), N(1), N(2), N(3), Y); end structural_2;