VLSI System Design Lecture: 1.3 COMS LOGICs

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Presentation transcript:

VLSI System Design Lecture: 1.3 COMS LOGICs Engr. Anees ul Husnain ( anees.buzdar@gmail.com ) Department of Computer Systems Engineering, College of Engineering & Technology, IUB

CMOS Logic The Inverter 1 n-MOS, 1 p-MOS When the inputs is '0,' the n-MOS transistor is OFF and the p-MOS transistor is ON. Thus the output Y is pulled up to '1' because it is connected to VDD but not to GND. Conversely, when A is '1/ the n-MOS is ON, the p-MOS is OFF, and the Y is pulled down to '0.'

CMOS Logic The NAND Gate It consists of two series n-MOS transistors between Y and GND and two parallel p-MOS transistors between Y and VDD. If either inputs or B is '0,' at least one of the n-MOS transistors will be OFF, breaking the path from Y to GND. But at least one of the p-MOS transistors will be ON, creating a path from Y to VDD. Hence, the output Y will be '1.‘ If both inputs are '1,' both of the n-MOS transistors will be ON and both of the p-MOS transistors will be OFF. Hence, the output will be '0.'

CMOS Logic The NAND Gate k-input NAND gates are constructed using k series n-MOS transistors and k parallel p-MOS transistors. TASKs !! Make the CMOS layout for Y = A . B . C Make the CMOS layout for Y = A + B + C

CMOS Logic The Combinational Logic In general when we join a pull-up network to a pull-down network to form a logic gate as shown in Figure 1.13, they both will attempt to exert a logic level at the output. When both try to exert a logic simultaneously than what happens ??

CMOS Logic The Combinational Logic The possible levels at the output are shown in Table 1.3. From this table it can be seen that the output of a CMOS logic gate can be in four states. The '1' and ‘0’ levels have been encountered with the inverter and NAND gates, where either the pull-up or pull-down is OFF the other structure is ON. When both pull-up and pull-down are OFF, the high-impedance or floating ‘Z’ output state results. This is of importance in multiplexers, memory elements, and bus drivers. The ‘crowiarred’ X level exists when both pull-up and pull-down are simultaneously turned ON. This causes an indeterminate level and also static power to be dissipated. It is usually an unwanted condition in any CMOS digital circuit.

CMOS Logic Connection & Behavior of Series & Parallel Transistors

Next… Compound Gates Pass Transistors & Transmission Gates Various implementations of a logic