Readout System of the CMS Pixel Detector J.C. Youth JC Yun Fermi National Acclerator Laboratory, Batavia, IL 60510, USA for the CMS Pixel Group It is a huge task to readout the CMS Pixel detector which has 66 million channels in the LHC environment. Many features are employed to ensure fast, low-noise, and robust communication throughout every stages of the readout chain. There are 2 main streams of communication. First the Data stream, FED accepts pixel data in forms of 6 level analog signal which contain pixel address and collected charge information. The digitized data are sent to the DAQ system through S-Link. Secondly the Control stream, the Pixel FEC (PixFEC) supplies clock and trigger information and provide data path for configuration settings to pixels via fast I2C bus. The Tracker FEC (TrkFEC) communicates with CCU for slow control, monitoring and timing distribution and also provides settings to the DOH, AOH and reads the DCU via slow I2C bus. Sensor and ROC (Readout Chip) * Zero suppression in pixel unit cell * Level 1 trigger required to read out * Sending hit information and receiving configuration data * Ability to adjust voltage levels to compensate chip-to-chip variation * Single Event Upset protected by capacitance * On-chip voltage regulator to compensate for any variation in load TBM (Token Bit Manager) : * Distributes control signal to ROC * Writes header and trailer * Controls readout through token pass * Stacks triggers awaiting token pass 3.2 mm 4.4 mm Analog Readout Analog Power Regulators Hub Stacks Control Sections 100m x 150 m pixel e- Charge collection Sensor + ROC Gate-Keeper * Prevents data reaching the TBM when not addressed * Sends signals back to DOH to keep signal level biased * When a “start” condition happens sends data to the TBM Particle path Panel / Blade Analog out bump bonding TBM LCDS ( Low Current Differential Signal) * Digital level translator from LVDS to small current differential mode * Fan-in and fan-out chips LCDS drivers L1A(trig, cal, sync, reset) Gate-Keeper CCU (Communication Control Unit) * Slow Control and Monitoring * Timing Distributions * Efficient redundancy scheme Slow I2C Service Tube I2C Slow I2C Delay ALT Port cards copper I2C TrkFEC Fiber (token ring) VME CCU DOH AOH DCU PLL Delay25 ALT (Analog Level Translator) * Amplifies and relays signal electrical Module / Panel CCU LVDSmux Slow I2C PLL Hard Reset CLK I2C Slow I2C DOH mDOH AOH optical Analog Out DOH (Digital Optohybrid) * Relaying control signal between CCU and FEC DATA CLK DATA CLK PLL (Phase Lock Loop) * Recovers clock and trigger from clock/trigger line * Adjustable Trigger Delay TrkFEC PixFEC Counting Room FED S-Link Trigger & Timing DAQ FED (Front End Driver) * Digitizes and Decodes Analog Signals * Repackages and sends to DAQ AOH (Analog Optohybrid) * Voltage Levels Chosen To Match ROC * Output Levels Fully Adjustable * Output Driver Identical to ROC FEC (Front End Controller) * Supplies Clock and Trigger information * Provide data path for configuration settings Data Decoding FIFO-I Read From VME DAC word Error Header Trailer FIFO-II (72 bits wide) Data Structure: Header Word Data0 | Data1 Data2 | Data3 . DataN | blank (1 of 8 fifo’s) TTC info (36 bit) Spy on DAC ADC Adjust Channel Offset Clocking Slew (8bits) “slices” Analog levels separation: RMS=2.5ADC Analog output in oscilloscope