Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. Chapter 5 Static MOS Gate Circuits Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved.

5.2 CMOS Gate Circuits

5.2 CMOS Gate Circuits

5.2.1 Basic CMOS Gate Sizing

5.2.1 Basic CMOS Gate Sizing

5.2.1 Basic CMOS Gate Sizing

(5.1) (5.2) 5.2.1 Basic CMOS Gate Sizing Equivalent width series stack : parallel stack : (5.1) (5.2)

5.2.2 Fanin and Fanout Considerations

5.2.2 Fanin and Fanout Considerations DeMorgan’s Laws (5.3)

5.2.2 Fanin and Fanout Considerations

5.2.2 Fanin and Fanout Considerations

5.2.2 Fanin and Fanout Considerations

5.2.3 Voltage Transfer Characteristics (VTC) of CMOS Gates

4.6.1 DC Analysis of CMOS Inverter

5.2.3 Voltage Transfer Characteristics (VTC) of CMOS Gates

5.3 Complex cmos gates

(5.4) (5.5) 5.3 Complex CMOS Gates Logic function exchanging AND, OR operations apply DeMorgans (5.4) (5.5)

5.3 Complex CMOS Gates

5.3 Complex CMOS Gates

5.4 xor and xnor Gates

5.4 XOR and XNOR Gates

5.5 Multiplexer Circuits

5.5 Multiplexer Circuits

5.6 Flip-Flops and latches

5.6.1 Basic Bistable Circuit

5.6.1 Basic Bistable Circuit Average propagation delay (5.6)

5.6.2 SR Latch SR Latch with NOR Gates

5.6.2 SR Latch SR Latch with NAND Gates

5.6.3 JK Flip-Flop

5.6.4 JK Master-Slave Flip-Flop

5.6.5 JK Edge-Triggered Flip-Flop

5.7 D Flip-flops and latches

5.7 D Flip-Flops and Latches

5.7 D Flip-Flops and Latches

5.7 D Flip-Flops and Latches

5.7 D Flip-Flops and Latches

5.7 D Flip-Flops and Latches

5.7 D Flip-Flops and Latches

5.7 D Flip-Flops and Latches

5.8 Power dissipation in CMOS Gates

5.8 Power Dissipation in CMOS Gates General power equation : (5.7)

5.8.1 Dynamic (Switching) Power

(5.8) (5.9) (5.10) 5.8.1 Dynamic (Switching) Power Average charging current : Power dissipation : (5.8) (5.9) (5.10)

5.8.1 Dynamic (Switching) Power

(5.11) 5.8.1 Dynamic (Switching) Power Time period : Average crowbar current : Average power : (5.11)

(5.12) (5.13) 5.8.1 Dynamic (Switching) Power Average power : (using switching activity factor ) (5.12) (5.13)

(2.32) (5.14) (5.15) (5.16) 5.8.2 Static (Stanby) Power (in Chapter 2) (basic diode equation) Leakage current : Static power dissipation : (pseudo-NMOS, low output) (2.32) (5.14) (5.15) (5.16)

(5.17) (5.18) 5.8.3 Complete Power Equation Power equation CMOS gate : pseudo-NMOS gate : (5.17) (5.18)

(5.17) (5.18) 5.8.3 Complete Power Equation Power equation CMOS gate : pseudo-NMOS gate : (5.17) (5.18)

5.9 Power and delay tradeoffs

(5.19) (5.20) 5.9 Power and Delay Tradeoffs (average power) (propagation delay) Power-delay product (PDP) Capacitor energy (5.19) (5.20)

(5.21) (5.22) (5.23) 5.9 Power and Delay Tradeoffs Energy-delay product (EDP) (propagation delay) using propagation delay (5.21) (5.22) (5.23)

(2.25) 2.5.2 Current Equations for Velocity-Saturated Devices Linear region operation (2.25)

2.5.2 Current Equations for Velocity-Saturated Devices Saturation region operation Limiting cases : ( ) ( ) (2.26) (2.27) (2.28) (2.29)

5.9 Power and Delay Tradeoffs

5.9 Power and Delay Tradeoffs

5.9 Power and Delay Tradeoffs Optimum EDP :

5.10 Summary

5.10 Summary Equivalent device width : Average propagation delay : Power : Complete power equation : (standard CMOS gate) (pseudo-NMOS gate) Energy-delay product :