THE MOS DEVICE

NMOS DESIGN Contact N+ Diff/Metal Clock property Source NMOS TiN Gate material Gate Drain Source Drain Gate N+ diff for nMOS THE MOS DEVICE

THE MOS DEVICE 2D CROSS SECTION OF THE NMOS DEVICE Low dielectric insulator Metal & contact to access to the Source SiO2 insulator .. and the Drain Source Gate which controls the channel Shallow Trench Isolation Drain

THE MOS DEVICE MOS STRAIN Starting 90 nm, introduction of strained silicon to speed-up the carrier mobility NMOS: Tensile strain Stretching the lattice allows the charges to flow faster The intrinsic mobility of electrons (supposed to be a physical constant) is INCREASED ! The main novelty related to the 90 and 65 nm technology is the introduction of strained silicon to speed-up the carrier mobility, which boosts both the n-channel and p-channel transistor performances. In Intel’s the 65 nm technology [8] the channel strains in both NMOS and PMOS devices have been improved over 90 nm technolgy. PMOS transistor channel strain has been enhanced by increasing the Ge content in the compressive SiGe film. Both transistors employ ultra shallow source-drains to further increase the drive currents. Let us the silicon atoms forming a regular lattice structure, inside which the electrons participating to the device current have to flow. In the case of electron carriers, stretching the lattice allows the charges to flow faster from the drain to the source. The mobility improvement exhibits a linear dependence with the tensile film thickness. A 80 nm film has resulted in a 10% saturation current improvement in Intel’s 90nm technology. The strain may also be applied from the bottom with a uniform layer of an alloy of silicon and germanium (SiGe). In a similar way, compressing the lattice slightly speeds up the p-type transistor, for which current carriers consist of holes (Fig. 6). The combination of reduced channel length, decreased oxide thickness and strained silicon achieves a substantial gain in drive current for both nMOS and pMOS devices.

THE MOS DEVICE METAL GATE – STARTING 65NM Highest mobility is obtained with optimized TiN/HfO2

THE MOS DEVICE IDS D G S MOS MODEL A MOS model is Made of equations describing IDS(VDS) and IDS(VGS) Based on parameters linked with the technology and given by the foundry IDS G S D Modeling the MOS device consists in writing a set of equations that link voltages and currents, in order to simulate and predict the behavior of the single device, and consequently the behavior of a complete circuit. For MOS devices, one of the key objective of the model is to evaluate the current Ids which flows between the drain and the source, depending on the supply voltages Vd, Vg, Vs and Vb. The equations represent the variation of the current Ids versus voltages in two different ways, as illustrated in the figure. The graphs are usually called “Ids/Vds”, “Ids/Vgs”. For simplicity, we consider that the voltage Vs is grounded. This assumption has no consequence on the results.

THE OLD MOS MODEL 1 5 parameters

THE MOS MODEL 3 10 parameters

MOS Model 3 takes into account the sub-threshold (VG<VTO) regime THE MOS MODEL 3 MOS Model 3 takes into account the sub-threshold (VG<VTO) regime MOS Model 3 takes into account temperature effects The difference may be upto 250% : Model 1 is far too optimistic; many saturation effects limit the Ion current Difference MOS Model 1, Model 3?

THE MOS MODEL BSIM4 0.35 V U0/2 0.25 V

THE MOS MODEL BSIM4

THE MOS MODEL BSIM4 20 key parameters listed in Microwind Details on BSIM4 equations in Microwind: Chapter 3 of the book

Roff ideally _____ Ron ideally ____ Ioff ideally _____ N-CHANNEL MOS AS A SWITCH Put a “___” (____V) Put a “___” (____V) Roff ideally _____ Ioff ideally _____ Ron ideally ____ Ion ideally _____ N-channel MOS behavior The expected behavior of the n-channel MOS device is summarized in the figure. The 0 on the gate should leave the drain floating. The 1 on the gate should link the drain to the source, via a resistive path. P-channel MOS behavior The expected behavior of the n-channel MOS device is summarized in the figure. The 0 on the gate should link the drain to the source, via a resistive path. The 1 on the gate should leave the drain floating. In other words, the p-channel transistor simulation features the same functions as the n-channel device, but with opposite voltage control of the gate.

How should I polarize to get Ion ? N-CHANNEL ION AND RON Where is Ron ? As IDS=150µA for VDS=1V, R= U/I=1/150µA, eq to 6Kohm. We gate Ion by VD=0, VS=1 (VDS=1), VG=1 (VGS=1) How should I polarize to get Ion ?

How should I polarize to get Ioff ? N-CHANNEL IOFF AND ROFF Where is Ioff ? IOFF is I(VDS=0), eq 10-9 A (1nA), for Vb=0.0 (upper curve). We get Ioff with VD=0, VG=0 (VGS=0) and VD = 1.0V for example How should I polarize to get Ioff ?

If you want to go faster, you can ask for more current MOS SIZING If you want to go faster, you can ask for more current More current: more W You may also reduce L, but by default, L= 2 lambda = Lmin The channel is the crossing between green and red (appears in orange in Microwind). W is the vertical size of the channel (the possible path of electrons) L is the horizonal size (the distance between drain and source for the electrons) Where is W, L ?

MOS SIZING Effect of 10 x Width Impact on Ion? Ion is proportionnal to W: if W is multiplied by 10, Ion is multiplied by 10 Impact on Ion?

THE MOS DEVICE ADD PROPERTIES FOR SIMULATION At each new Clock, the period increased by 2 “Visible” (eye) is added to view the Source node

THE MOS DEVICE NMOS SWITCHING Drain Source You understand this, you understand everything…. Gate 0-0.1s: the gate is OFF, no channel. The source is floating: Microwind sets node to 0.0 by default 0.1-0.2: The gate is ON, a channel exists. The source is connected to drain eq. to 0.0. 0.2-0.3: at the same time we close the channel, we change the drain. The source starts to follow and then floats. The capacitance effect of the Pwell/N+Diff is the key component for the analog memory effect. The voltage can be stored several ms (depends on Ioff leakage current) 0.3-0.4. Channel is ON. Source cannot reach VDD because of VT effect, around 0.35V 0.4-0.5. Channel is OFF: source is floating, memory effect at VDD-VT 0.5-0.6. Channel is ON. Good 0 at Source. Interpretation

THE MOS DEVICE NMOS SWITCHING SYNTHESIS 1 1 Good 0 Poor 0 Voltage 1 Good 0 Poor 0 Voltage Good 1 Poor 1 Good 1 1 1.0 0= No Channel 1= Channel: If I want to pass a 0, I get a good 0; if I want to pass a 1, I get a poor 1 (VDD-VT) Poor 1 Undetermined 0.5 What’s your choice ? Poor 0 Good 0 0.0

THE MOS DEVICE PMOS DESIGN PMOS Source Gate pMOS = TiN & P+diff & nwell Drain .. & N+diff to access the nwell .. & VDD to polarize the nwell so that diodes are in inverse mode

THE MOS DEVICE PMOS DESIGN – POLARIZATION ERROR Oups, I forgot the Nwell polarization contact (N+Diff/Metal) If you make a mistake in the well polarization, you may destroy the chip (VDD/VSS short-circuit) ! .. Or I forgot to add VDD property to polarize the well properly I cancel simulation and add the N+diff/Metal contact as well as the VDD property on it

THE MOS DEVICE PMOS STRAIN Compressive strain Compressing the lattice slightly speeds up the p-type transistor The intrinsic mobility of holes (suppose to be a physical constant) is INCREASED !

PMOS - WELL POLARISATION VDD for well polarization PN junction in inverse mode Should ALWAYS be in reverse mode Why? Why: Because P-substrate is connected to VSS (ground, 0V) by the back side automatically. The N source ranges from 0 to 1.0V or more; always larger or equal to substrate polarization (0). How: put VDD (highest potential) on well How?

THE MOS DEVICE PMOS SWITCHING When Vgate is at 0, the channel is ON. The pMOS cannot pass 1 properly, the Vout voltage cannot go lower than VT. However, the 1.0 on the drain leads to a perfect 1.0 on the source when Vgate=0.

PMOS SWITCHING SYNTHESIS 1 1 Good 0 Poor 0 Good 1 Poor 1 1 1= No Channel 0= Channel: If I want to pass a 0, I get a poor 0 (VT); if I want to pass a 1, I get a good 1 What’s your choice ?

Otherwise, there is a risk of damage CONTACTS There should be as many contacts as possible (2 x 2 lambda, distance 3 or 4 lambda) Otherwise, there is a risk of damage Because 1 contact acts as a fuse for currents above 1mA. The contact just melts and the electrical connection is destroyed. This is in fact used for security card encryption for example. Contacts are 2x2 lambda, seperated by 3 lambda. Put as many as you can for reliability purpose. Why ?

POOR DESIGNS Extension of diffusion after contacts loads the node by extra capacitance. A large gate makes L large, so Ion is reduced. N+ polarization contact can touch P+ diff, but should never overlap. For manufacturability, diff area should be as simple a possible (ideally rectangular) Contacts need 2 lambda distance to gate. Why ?

THE MOS DEVICE DESIGN RULE CHECKER Help > Design Rules Rules are more or less the same whatever the technology Gate should be 2 lambda length Metal should be 3 lambda Etc..

THE MOS DEVICE BIG WIDTH Parallel MOS are much better than a tall single MOS Parallel MOS tolerate process variability

THE MOS DEVICE N-CHANNEL IOFF/ION The process variations make a non-unique IOFF/ION point random distribution of points. ION is around 1mA/µm with IOFF 10nA/µA (45nm) “Low leakage” MOS, which is the default MOS device

Low leakage High Speed High Voltage MOS DESIGN New kind of MOS introduced starting 0.18µm Low Leakage, medium speed, by default High Speed: for critical path in terms of speed High Voltage: for I/O which need higher voltage (oxide thicker than the others MOS) A new kind of MOS device has been introduced in deep submicron technologies, starting the 0.18µm CMOS process generation. the new MOS, called “low leakage” or “High-Vt” MOS device is available as well as the normal on, recalled “high-speed MOS”. For I/Os operating at high voltage, specific MOS devices called “High voltage MOS” are used. We cannot use high-speed or low leakage devices as their oxide is too small. A 2.5V voltage would damage the gate oxide of a high-speed MOS in 0.12µm technology. The high voltage MOS is built using a thick oxide, two to three times thicker than the low voltage MOS, to handle high voltages as required by the I/O interfaces.

Low leakage IDS High Speed IDS Ion High Voltage IDS VGS = VGS = VGS = MOS DESIGN Low leakage IDS VGS = VDS High Speed IDS Ion VGS = VDS High Voltage IDS VGS = VDS Low leakage The main drawback of the “Low leakage” MOS device is a 30% reduction of the Ion current, leading to a slower switching. High speed MOS devices should be used in the case of fast operation linked to critical nodes, while low leakage MOS should be placed whenever possible, for all nodes where a maximum switching speed is not required. High voltage The I/V Characteristics of the high voltage MOS are plotted in figure xxx, for Vgs and Vds up to 3.3V. The channel length is 0.3µm, channel width 1.2µm. There are two main reasons to keep a low-voltage supply for the core of the integrated circuit. The first one is low-power consumption, which is of key importance for integrated circuits used in cellular phones or any portable devices. Low supply strongly reduces power consumption by reducing the amplitude of signals, thus reducing the charge and discharge of each elementary node of the circuit. The second reason for low internal supply is the oxide breakdown. Increased switching performances have been achieved by a continuous reduction of the gate oxide thickness. In 0.12µm technology, the MOS device has an ultra thin gate oxide, around 0.003µm, that is 3nm or 30 Å,. Speed: ION : IOFF : Speed: ION : IOFF : Double L & Tox Used for IOs Also some analog cells

Microwind’s Low Leakage NMOS (RVT) Microwind’s High speed NMOS (SLVT) MOS VARIANTS IN 20-NM Ion=1.1mA Ion=0.9mA Microwind’s Low Leakage NMOS (RVT) Microwind’s High speed NMOS (SLVT)

THE MOS DEVICE MOS DESIGN Why we should be careful with high speed MOS Small Ion penalty Ioff ~10nA Ioff ~100pA Huge Ioff reduction High speed Low leakage The main objective is to reduce significantly the Ioff current, that is the small current that flows from between drain and source with a gate voltage 0 (Supposed to be no current in first order approximation). On the figure below, the low leakage MOS device (right side) has an Ioff current reduced by a factor 50, thanks to a higher threshold voltage (0.45V rather than 0.35V). Low leakage MOS has higher VT, slight Ion reduction Low leakage MOS has 1/100 IOFF of high speed MOS Virtex 7 leakage ?

Option layer properties MOS DESIGN THE MOS DEVICE Option layer Double click Simple access to low leakage, high voltage and isolated Pwell Option layer properties

THE MOS DEVICE TECHNOLOGY VARIANTS General Purpose (Mobile) High Performance (PC) Low power (MP3) Microwind targets the upper part of General Purpose, lower part of High Performance Microwind tech files exploit Intel data and publications There may exist several variants of the 65-nm process technology. One corresponds to the highest possible speed, at the price of a very high leakage current. This technology is called “High speed” as it is dedicated to applications for which the highest speed is the primary objective: fast microprocessors, fast DSP, etc. This technology has not been addressed in Microwind’s 65nm rule file. The second technological option called “General Purpose” (Fig. 3) is targeted to standard products where the speed factor is not critical. The leakage current is one order of magnitude lower than for the high-speed variant, with gate switching decreased by 50%. There may also exist a third variant called low leakage (bottom left of fig. 3-a). This variant concerns integrated circuits for which the leakage must remain as low as possible, a criterion that ranks first in applications such as embedded devices, mobile phones or personal organizers. The operational voltage is usually from 0.85V to 1.2V, depending on the technology variant. In Microwind, we decided to fix VDD at 1.0V in the cmos65nm.RUL rule file, which represents a compromise between all possible technology variations available for this 65-nm node. Test your switch

THE MOS DEVICE THE PERFECT SWITCH The transmission gate: a perfect swicth: G=0 1 0 or 1 Good 0 or Good 1 G=1 The Perfect switch Both NMOS devices and PMOS devices exhibit poor performances when transmitting one particular logic information. The nMOS degrades the logic level 1, the pMOS degrades the logic level 0. Thus, a perfect pass gate can be constructed from the combination of nMOS and pMOS devices working in a complementary way, leading to improved switching performances. Such a circuit is called the transmission gate. The transmission gate let a signal flow if en=1 and /en=0. In that case both the n-channel and p-channel devices are on. The n-channel MOS transmits low voltage signals, while the p-channel device preferably transmits high voltage signals. The main drawback of the transmission gate is the need for two contraol signals Enable and /Enable, thus an inverter is usually required. Transmission gate: combination of PMOS and NMOS working in complementary way NMOS transmits low voltage and PMOS transmits high voltage

THE PERFECT SWITCH The Perfect switch Both NMOS devices and PMOS devices exhibit poor performances when transmitting one particular logic information. The nMOS degrades the logic level 1, the pMOS degrades the logic level 0. Thus, a perfect pass gate can be constructed from the combination of nMOS and pMOS devices working in a complementary way, leading to improved switching performances. Such a circuit is called the transmission gate. The transmission gate let a signal flow if en=1 and /en=0. In that case both the n-channel and p-channel devices are on. The n-channel MOS transmits low voltage signals, while the p-channel device preferably transmits high voltage signals. The main drawback of the transmission gate is the need for two contraol signals Enable and /Enable, thus an inverter is usually required.