Sub-nanosecond Time Synchronization Mechanism for Radio Interferometer Array E. H. Ait Mansour 1, B. Da Silva 1, S. Bosse 1 and K-L. Klein 2 1 Observatoire de Paris, Station de Radioastronomie de Nançay, Nançay, France 2 Observatoire de Paris, LESIA, Meudon, France 4 th IEEE International Workshop M&N 2017 Naples, Italy September 27-29, 2017

Outline Nançay Radio Interferometer Array Time synchronization protocols Delay model Proposed Time Synchronization Algorithm Algorithm Performance and Limitations Conclusion & Further Works

Nançay Radio Interferometer Array 3,2km Wavelength : m Frequency band : MHz Maximal baseline : 3.2 km Number of antenna : 48 Antenna diameter : m 3.2 km 2.5 km

Time synchronization protocols Symmetric link assumption Uncertainty increase with network length

Delay model Master/slave architecture Slave 1 Slave 2 Slave 3 Slave 4 Slave N-1 Slave N d1d1 d2d2 d N-1 Master Various distances between master and slaves Star topology, distributed clocks Digitizers clocks for each antenna need Time Synchronization N x Clk

Delay model d MM d MS d SM d : Round-trip delay (Master to Master delay) d : Master to Slave delay d : Slave to aster delay R : Reception, T : Transmission, C : Channel Asymmetric link MM MS SM

Delay model Clocks adjustment Without Adjustment : A-1 : Clocks at Master side A-2 : Clocks at slaves sides With adjustment B-1 : Clocks at Master slides B-2 : Clocks at slaves sides DL : Programmable Delay Chip 1:N : Clock divider

Proposed Time Synchronization Algorithm Asymmetric link

Proposed Time Synchronization Algorithm Delay difference between each pair of slave : Round trip delay with adjustment Synchronization condition

Proposed Time Synchronization Algorithm Synchronization condition We introduce d x1 and d x2 in the path of clocks to get synchronization : How to compute d xi ?

Proposed Time Synchronization Algorithm Adjustment values vector The last value of the vector is set as reference (d xN = 0)

Proposed Time Synchronization Algorithm Example : Quad-channel clocks synchronization Computation of the vector parameters for 4 antennas. Accuracy of round trip delay measurement supposed equal to 13 ps (1 LSB). Step 1 : Round trip delays measurement for each channel T2= 8, T1 =5, T4= 15 T3=13 Step 2 : Delays sorting T1= 5, T2 =8, T3= 13 T4=15 Step 3: computation = 3 = 2 = 5 Step 4: computation

Proposed Time Synchronization Algorithm Example : Quad-channel clocks synchronization Step 5 : Adjustment

Proposed Time Synchronization Algorithm Asymmetric error minimisation

Algorithm Performance and Limitations

Synchronization period vs. number of slaves (N) for different values of algorithm parameter µ

Algorithm Performance and Limitations µµ 0 (N=10)µ 0 (N=100)µ 0 (N=1000) * * *10 -3 Offset mean error µ 0 (ps) after calibration versus number of slaves N

Conclusion & Further Works The main result of this research is an iterative algorithm for delays computation and compensation with sub-ns accuracy. The proposed algorithm proved to good results for asymmetric link delay error minimization with fiber optics link assumption, but the algorithm can be used in distributed networks with various link type and length respecting Master/Slaves architecture. The synchronization period and accuracy can be controlled with algorithm parameters. This algorithm can achieve accuracy better than 10~ps. Besides, real time hardware or software implementation may be possible and computational complexity is reduced comparing with algorithms developed previously Quad-channel hardware Implimentation is ongoing using TDC (Time-to-Digital Converter) with 13 ps accuracy for round-trip delays measurement and FPGA for offsets computation and adjustment.