SOLEIL Fast Orbit Feedback System Architecture and FPGA implementation Nicolas HUBERT Synchrotron SOLEIL On behalf of Diagnostics group 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA Summary FOFB principle FOFB architecture FPGA implementation Generalities Communication Matrix multiplication PI Controller Latency FPGA resources 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA FOFB principle An ‘all embedded’ solution All the processing of the FOFB is done in the Libera FPGA, on top of the position calculation provided by Instrumentation Technologies FA position data from other Liberas Current set point to power supplies Configuration /monitoring 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA FOFB principle (2) dedicated power-supplies FRONT BPM BACK 48 dedicated air coil correctors over stainless steel bellows at each side of the straight sections. 3-4/04/2008 2nd Libera Users Meeting, ALBA

Inversed response matrix (SVD) FOFB architecture (1) Processing is done in 48 Liberas (1 per corrector) using the FPGA resources. 1 column ΔXi or ΔZi 120 columns 120 lines 1 line line 1 120 columns 1 column 1 column ΔXi or ΔZi 120 columns 120 lines Inversed response matrix (SVD) ΔXi or ΔZi 48 lines 1 line line i 120 lines 1 column ΔXi or ΔZi 120 columns 120 lines 1 line line 48 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA FOFB architecture (2) CELL N To cell N+1 LIBERA Air-coil magnet POWER SUPPLY LIBERA LIBERA LIBERA POWER SUPPLY LIBERA LIBERA Air-coil magnet To cell N-1 LIBERA 2 conductor copper cable Optic link Copper link RS485 link 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA FOFB architecture (3) Libera rack (7 or 8 units) Power supply rack (2 or 4 units) Air-coil magnet (2 planes) Optic fiber RS 485 link 2 conductor copper cable 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Generalities All the FPGA programming has been done using textual code: Instrumentation Technologies part => Verilog Soleil part => VHDL Simulation with Modelsim 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Data processing Instrumentation Technologies FPGA design CC Rocket I/Os Cx Cz Matrix multiplication Control RS 485 PI controller ΔX, ΔZ Rx, Rz ΔIx ΔIz Ix fofb_top 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Communication Communication Controller: Designed by Diamond Light Source (I. Uzun). Allows the distribution of all FA data to every Libera. All 120 Liberas are connected to the dedicated network for a global feedback. Protocol is topology independent Start of time frame: each Libera sends its X and Z data to all neighbours over the network When receiving a new packet, CC stores data and sends them to all neighbours If the packet has already been received, it is discarded. 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Communication RS 485 serial link to power supplies: One way communication: Libera => power-supply Simple protocol: 22 bits per frame: 16 bits for data (15 bits+1 for the sign) 2 bits for parity 4 bits for synchronization (start/stop) Link rate is 1.25 Mbits/s Transmission delay is around 20 µs 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Matrix multiplication Performed by a 120 cycles Multiply Accumulator Core Generated by Coregen utility from Xilinx Multiplications are done serially for one plane The same core used for both planes, one after the other BRAM 120 R-1X R-1Y ΔX ΔY Multiply Accumulator Core result ready Registers ΔIX ΔIZ 3-4/04/2008 2nd Libera Users Meeting, ALBA

previous current setting Matrix multiplication result FPGA Implementation: Controller PI controller is used Proportional coefficient is not implemented in the FPGA the inverse response matrix is multiplied by the right coefficient before being sent to the FPGA Integrator part is an accumulator with a configurable coefficient IN = ΔIN + coeff * IN-1 Next current setting previous current setting Matrix multiplication result 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Rounding after division All values in the data processing are integers All parameters are multiplied by a power of 2 and rounded before being sent to the FPGA in order to have a good enough precision as an integer. => Result needs to be divided by the same value With a power of 2, the division is easy => Suppression of less significant bits With 2’complement coding method this division rounded the result to the lower integer Example: division by 2^2 +15  00001111 gives 000011 + 3 - 15  11110001 gives 111100 - 4 Introduction of a noise with a non-zero mean value: - No effect if all singular values are kept when inverting the matrix - Drift of the correctors current if not 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Monitoring Fast Feedback Application Interface (provided by I-Tech) allows retrieving 8 32-bit data from Fast Feedback Application to control system at SA rate (~10 Hz). => Monitoring of the setting points sent to the power supplies - mean value - min/max detection over 1024 timeframes Va, Vb,Vc, Vd, X, Y, Q, Sum average IX, IZ min/max IX IY unused 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA Processing latency Position processing 190 µs Data Distribution 60 µs Matrix Multiplication 5 µs PI controller 1 µs Serialization and transmission to PS 20 µs FPGA delay ~280 µs Power supply latency Eddy currents in vacuum chamber ~60 µs 3-4/04/2008 2nd Libera Users Meeting, ALBA

FPGA Implementation: Resources Design Summary -------------- Number of occupied Slices: 11,078 out of 13,696 80% Number of Block RAMs: 119 out of 136 87% Number of MULT18X18s: 72 out of 136 52% Lack of multipliers in the FPGA (sharing the same resources as 32 bits Block RAM) Numbers of Rocket I/O ports is limited to 2. No redundancy in the dedicated network (simple ring for the moment). If one link fails, the packet doesn’t have enough time to reach all BPMs. In this case data propagation >90 µs Neutrino_dsc_crosstalk_comp.v block uses 16 multipliers and 16 BRAMs (16 bits) =>As this block is inefficient for crosstalk compensation, I-Tech must have removed it in release 1.80 3-4/04/2008 2nd Libera Users Meeting, ALBA

2nd Libera Users Meeting, ALBA FOFB Sniffer Allows to record and retrieve Fast Acquisition data from the dedicated network to the control system. Verification of the good communication Spectrum analysis of the beam noise Implementation Commercial card to be implemented in a compact PCI Same behaviour than the Libera except there is no own data injected on the network. Can record on demand up to 30 seconds of continuous FA data 3-4/04/2008 2nd Libera Users Meeting, ALBA