Presentation on FPGA Technology of Presented to:- Presented By:- Dr. S.C. Jain Hamendra Singh Professor CSE Dinesh Jain Deepti Meena Jeetesh

Introduction Altera was the first to introduce the 8-input fracturable look-up table (LUT) with the Stratix® II family in 2004. At its core is the adaptive logic module (ALM) with 8 inputs. As a result, Altera FPGA architecture is at least one generation ahead of the competition, and routing architecture is two generations ahead.

Adaptive Logic Module(ALM) The key to the high-performance, area-efficient architecture is the ALM. The ALM has 1.8X density advantage over the competition. The ALM can implement a full 6-LUT or select 7 input function.

Adaptive Logic Module(ALM)

ALM The combinational portion has eight inputs and includes a LUT that can be divided between two adaptive LUTs (ALUTs) using Altera’s patented LUT technology. The ALM can implement various combinations of two functions as follow.

Designing of ALM Experiments showed that a 6-LUT could yield a 14% performance increase over classical 4-LUT, But with a penalty of 17% area increase, Due to the Larger number of inputs and LUT mask. To implement a k-input LUT (k-LUT) i.e. LUT that can implement any function of k inputs—2k SRAM bits and a 2k:1 multiplexer are needed.

Delay-Cost Tradeoff with LUT Size

Problems with large number of I/Ps It increases the size of the LUT. It increases Cost of the LUTs. But Most Importantly in large LUTs we can’t implement smaller functions efficiently.

THE ALM To overcome problems associated with large I/P size LUTs Altera Designed ALM such that it can be divided into smaller LUTs, implementing more than one smaller functions. The ability to divide a LUT is what makes it “adaptive.”

Comparing the Stratix II ALM and the Virtex-5 LUT-Flipflop Pair

ALM vs. Virtex-5 LUT Flexibility

Implementing 5- and 3-Input Functions in Stratix II ALM

Implementing 5- and 3-Input Functions in Virtex-5 LUT-Flipflop Pair

Density Results

Routing Architecture The Stratix series of devices introduced the MultiTrack interconnect to maximize connectivity and performance. The routing architecture provides the connectivity between different clusters of logic blocks, called logic array blocks (LABs). It can be measured by the number of "hops" required to get from one LAB to another. The fewer the number of hops and more predictable the pattern, the better the performance and the easier it is for CAD tool optimization.

The Stratix and Stratix II families use a three-sided routing architecture as shown in Figure The Virtex architectures use a 2-sided routing architecture

Stratix and Stratix II Connectivity

Conclusion Altera FPGA architecture is unmatched in the industry and is at least one generation ahead of the competition in terms of logic architecture and two generations ahead in terms of routing architecture.

References Altera “White Paper FPGA Architecture”. Lewis, D., et al. “The Stratix II Logic and Routing Architecture.” FPGA 2005: ACM Symposium on FPGAs, 14-20.February 2005.