… General Decoder for a Linear Block Code … … Received vector buffer register r r … r0 r1 rn-1 Syndrome calculation circuit General Decoder for a Linear Block Code … s0 s1 sn-1 Error-pattern-detecting circuit … e0 e1 en-1 r0 r1 rn-1 + + + v0 v1 vn-1 Corrected Output

CS501 Advanced Computer Architecture Lecture 33 Dr.Noor Muhammad Sheikh

Review

Operating System Interface

Parity Check Code

Hamming code

Redundant Array of Independence Disk

Hamming Code First class of linear codes devised for error correction

For any positive integer m<=3 ,a Hamming code with following parameters exists: Code Length: n=2m-1 Number of information symbols: k = 2m-1-m Number of parity-check symbols: n – k = m

Example For m=3, The parity-check matrix of Hamming code is (7,4) linear code.

Example: Encode 1011 Using the Hamming Code and Odd Parity Insert the data bits: P1 P2 1 P4 0 1 1 P1 is computed from P1 Å D3 Å D5 Å D7 = 1, so P1 = 1. P2 is computed from P2 Å D3 Å D6 Å D7 = 1, so P1 = 0. P4 is computed from P1 Å D5 Å D6 Å D7 = 1, so P1 = 1. The final encoded number is 1 0 1 1 0 1 1.

Example : Compute the Odd Parity SECDED Encoding of the 8-bit value 01101011 The 8 data bits 01101011 would have 5 parity bits added to them to make the 13-bit value P0 P1 P2 0 P4 1 1 0 P8 1 0 1 1. P1 = 0, P2 = 1, P4 = 0, and P8 = 0 we can compute that P0, overall parity, = 1, giving the encoded value: 1 0 1 0 0 1 1 0 0 1 0 1 1

CRC Generator Based on the Polynomial x16 + x12 + x5 + 1 1 2 3 4 5 6 7 8 9 1 1 1 1 2 1 3 1 4 1 5 Data

The number and position of XOR gates is determined by the polynomial. CRC does not support error correction but the CRC bits generated can be used to detect multibit errors. The CRC results in extra CRC bits, which are appended to the data word and sent along. The receiving entity can check for errors by recomputing the CRC and comparing it with the one that was transmitted.

RAID Level 0 … … … … Strip8 Strip4 Strip12 Strip0 Strip1 Strip10

RAID Level 0 Not a true member of the RAID family. Does not include redundancy to improve performance.

In few applications, capacity and performance are primary concerns than improved reliability. So RAID level 0 is used in such applications.

RAID Level 0 The user and system data are distributed across all the disks in the array. Notable advantage over the use of a single large disk. Two requests can be issued in parallel, requesting the I/O queuing time.

Performance of RAID Levels Performance of RAID Levels depends upon two factors: Request pattern of the host system Layout of the data

RAID Level 2 b0 … b1 … b2 … b3 … f0 (b) … f1(b) … f2(b) …

RAID Level 3 b0 … b1 … b2 … b3 … P (b) …

RAID 2 and RAID 3 Make use of parallel access techniques. All member disks participate in execution of every request. Spindles of the individual drives are synchronized

RAID 2 and RAID 3 Data striping is used. Strips are as small as a single byte or word. In RAID 2, error-correcting code is calculated across corresponding bits on each data disk.

Difference between RAID2 and RAID 3 RAID 3 requires only a single redundant disk. Instead of an error-correcting code, a simple parity bit is computed for the set of individual bits in RAID 3

RAID Level 4 … … … … … Block8 Block4 Block12 Block0 Block1 Block2 P(8-11) P(4-7) P(12-15) P(0-3) … Block5 Block6 Block7 Block9 Block10 Block11 Block13 Block14 Block15 … … …

RAID Level 5 … … … … … Block8 Block4 Block12 Block0 Block1 P(12-15)

RAID Level 4 Make use of independent access technique. Both RAID levels 4 and 5 are suitable for those applications which require high I/O requests rates, and less suitable which require high data rate transfer. Data striping is used. A bit-by-bit parity strip is calculated across corresponding strip on each data disk.

RAID 4 Involves a write penalty when an I/O write request of small size is performed. To calculate the new parity, the array management software must read the old user parity strip.

RAID 4 Each strip involves two reads and two writes. For large size I/O writes, parity is easily computed by calculation using only the new data bits. Parallel drives can be updated in parallel with data drives.