Status of PLL system of ALS

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Presentation transcript:

Status of PLL system of ALS Shogo Kambara, Yoshiki Moriwaki, Kazuya Yokogawa, Satoshi Yoshioka, Tatsunari Sawada, Shuhei Miyata University of Toyama f2f meeting@ University of Toyama

Contents ALS PLL system Fiber noise Experiment of PLL system

Arm Length Stabilization (ALS) PDH PD 40Mhz EOM Optical fiber PLL SHG AOM Laser 2 PD PR2 BS X-Armcavity Laser 1 PR3

PLL system 40MHz To Arm cavity Single-mode fiber To Michelson Main Laser Green Laser PD Synthesizer Single-mode fiber Beatnote To Michelson To Arm cavity PZT

PLL system Using a optical fiber for beatnote To Arm cavity 40MHz PLL Main Laser Green Laser PD Synthesizer Single-mode fiber Beatnote To Michelson To Arm cavity PZT Using a optical fiber for beatnote Easy aligment To save space of PSL table

PLL system Problem Noisy Using a optical fiber for beatnote 40MHz PLL Main Laser Green Laser PD Synthesizer Single-mode fiber Beatnote To Michelson To Arm cavity PZT Using a optical fiber for beatnote Easy aligment To save space of PSL table Problem Noisy

PLL system Problem Noisy Check the fiber noise 40MHz PLL Main Laser Green Laser PD Synthesizer Single-mode fiber Beatnote To Michelson To Arm cavity PZT Using a optical fiber for beatnote Easy aligment To free up space of PSL table Check the fiber noise Problem Noisy Single-mode fiber

Measurement of fiber noise I measured power of beam for 10 minutes

Transmittance

Summary When optical fiber is shaked, the poralization of beam is rotating Future work I will use POLARIZED WAVE HOLDING OPTICAL FIBER which is more stable.

Experiment of PLL system Beatnote Frequency divider Beatnote is locked at 129MHz

Result Unlock FWHM:100Hz 128.998680MHz 10MHz Lock! 180s Beatnote Lock! 180s Unlock 10MHz Feedback signal to PZT (1MHz/V)

Summary We maintain frequency locking for 3 minutes. Line width is about 100Hz. The position of peak is shifted 1.3kHz from 129Mhz What are these sideband? Future work upgrade I will upgrade the filter circuit of PLL for long time locking. I will calculate the requirement of PLL system