Problems with “Inferred Latches” in Verilog

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Presentation transcript:

Problems with “Inferred Latches” in Verilog ECE 111

The “Inferred Latch” Problem In a combinational always statement, always@(*), and functions, “case” and “if-then-else” statements must be completely specified for all signals. If not, Quartus will generate asynchronous “latches”, which are BAD (and NOT ALLOWED for the RLE and SHA1 projects) !!

The “Inferred Latch” Problem Asynchronous “latches” are BAD for the following reasons: Most (if not all) industry chip designs follow a “synchronous” design methodology where all flip-flops must be controlled by the same clock. Not all FPGAs and ASIC cell libraries support asynchronous latches. Difficulty with timing closure and accurate timing analysis. Unpredictable behavior.

Example: latch_case_problem.v

Example: latch_case_problem.v

Example: latch_case_problem.v asynchronous latches are BAD and not allowed

Example: latch_if_problem.v

Example: latch_if_problem.v

Example: latch_if_problem.v asynchronous latches are BAD and not allowed

Make Sure Your Designs Do Not have Inferred Latches