KM3NeT CLBv2

LM32_2nd integration issues LM32_2nd is Master and is able to access LM32_wrpc memory space at addresses 0x00100000-0x00130000 Maybe later: Implement the other way around as well Extend the LM32 memory a bit to accommodate some common address space for semaphores etc. 0x00130000 SDB 0x00120800 SDB IO 0x00120000 Master MEM 0x00100000 MEM S LM32 2nd M WB Crossbar (2x3) LM32 WRPC (3x2) 0x00030000 0x00040000 SDB SDB 0x00030000 SDB 0x00020800 SDB Slave IO IO 0x00020000 0x00020000 MEM 0x00000000 MEM 0x00000000

XST and Precision Throughout the WRPC vhdl code a lot of undefined “X” are used when an assignment is done that is in fact don’t care. Fine! Examples are files: ....fw\WRPC\modules\wr_endpoint\ep_wishbone_controller.vhd and ....fw\WRPC\modules\wr_endpoint\ep_pcs_tbi_mdio_wb.vhd.vhd We that the "stat bts" command (=show bitslide value) always gave the wrong value 31 x 800ps = 24800 ps when Precision was used. But… The correct value for bitslide is in simulation and on the debug LEDs. Our first assumption was that, when using Precision Synthesis, “X” is chosen either “1” or “0” which is in fact okay according to the VHDL sources. However, if XST always translates “X” into “0” and the WR software isn't taking care of proper masks then one ends up in the situation that software behaves differently for a bit file that was made using XST or Precision.

How low can you go… But, It turned out not to be a matter of ‘’X’’ and ‘’0’’…

Found a bug in ep_wbgen2_pkg due to XST versus Precision File wr_endpoint.vhd contains this statement to merge the different register outputs from the various sub designs (“ep”= endpoint, “tsu”= time stamping unit, “rpath”= receive path, “dmtd” = dual mixer time difference). regs_towb <= regs_towb_ep or regs_towb_tsu or regs_towb_rpath or regs_towb_dmtd; Note that “or” is an overloaded function, defined in package “ep_wbgen2_pkg” (file ep_registers_pkg.vhd). “or” uses “f_x_to_zero” to define “undefined” signals. function f_x_to_zero (x:std_logic) return std_logic is begin if(x = 'X' or x = 'U') then return '0'; else return x; end if; end function;

Found a bug in ep_wbgen2_pkg due to XST versus Precision if(x = 'X' or x = 'U') then return '0'; else return x; This doesn’t cover all cases and leads to this (rather vague) warning: # Warning: [45431]: “WRPC/modules/wr_endpoint/ep_registers_pkg.vhd", line 194: All equality comparisons with 'X', 'W', 'U' or 'Z' are treated as FALSE. This can potentially lead to simulation mismatch. This is what the function is meant to do: function f_x_to_zero (x:std_logic) return std_logic is Begin if x = '1' then return '1'; Else return '0'; end if; end function;

Stream Selector (IPMUX) Packet Transmit IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Rx Stream Select Flags RxPort_m Management & Control aux_master S 6 1 7 Pause Frame Management & Config. State Machine 5 ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Done! Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs 2nd CPU LM32 M SPI S S Xilinx Kintex-7 MEM S WB Crossbar (2x3) S M UART S I2C I2C S GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus

Stream Selector (IPMUX) Packet Receive Done! IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs 2nd CPU LM32 M SPI S S Xilinx Kintex-7 MEM S WB Crossbar (2x3) S M UART S I2C I2C S GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus

Next: Connect IPMUX management IP and MAC addresses, UDP port numbers IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control aux_master S 6 1 State Machine 5 7 Pause Frame Management & Config. ADC Fifo 4 Hydrophone 2 3 Done! TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (2x3) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus

Currently: integrate & connect LM32_2nd (FIFO interface) CPU_Tx Simulation okay CPU_Rx Simulation okay Next hardware implementation and test. IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_mac2buf Rx_buf2data Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs 2nd CPU LM32 M SPI S S Xilinx Kintex-7 MEM S WB Crossbar (2x3) S M UART S I2C I2C S GPIO S Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus

Stream Selector (IPMUX) Status IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPacket Buffer 64KB RxPort 1 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 wrf_src Rx_mac2buf Rx_mac2buf Rx_buf2data wrf_snk Flags RxPort_m Management & Control aux_master S 6 1 Management & Config. State Machine 5 7 Pause Frame ADC Fifo 4 Hydrophone 2 3 TxPacket Buffer 32KB TxPort 1 Management & Control TxPort 2 S Tx_pkt2mac Tx_pkt2mac Tx_data2buf Tx Stream Select Multiboot 1 2 Flags TxPort_m S Management & Control Nano Beacon ext_wb S WB Crossbar (1x8) M M M S M M M M M M Debug LEDs WB Crossbar (2x3) S M 2nd CPU LM32 M SPI S UART S S S S Xilinx Kintex-7 MEM S I2C I2C GPIO Data UTC time & Clock (PPS, 125 MHz) Control Point to Point interconnection SPI Flash Debug RS232 Temp Compass Tilt Wishbone bus

Timing Servo Phase tracking Fine time stable Calibration of various delay constants should be done This involves a thorough study of the timing system… Pulse Per Second (PPS) on the master (SPEC) PPS on the slave (KC705 + SoftPLL_FMC) Open issues (further study needed): Reset button on the KC705 puts the system in a weird state

Status Listing Done: Currently: To do (in order of priority): LM32 + WB-Crossbar + DPRAM + UART Soft-PLL FMC layout WR without PCI-express Deterministic PHY 1-wire Endpoint (= MAC) Fabric redirector Currently: Intergrating / Connecting LM32_2nd Soft PLL (hardware + software). Still under study… Calibration procedure PPS generator To do (in order of priority): Mini-nic <= Complex, but seems to work (no further action at the moment) SysCon <= easy (no further action at the moment) LM32 debugger