Memory The programmer’s model .text, .data .ktext, .kdata

Slides:



Advertisements
Similar presentations
Datorteknik OperatingSystem bild 1 the Operating System (OS)
Advertisements

Datorteknik VirtualMemory bild 1 Virtual Memory User memory model so far: Separate Instruction and Data memory In reality they share the same memory space.
Datorteknik MainMemory bild 1 Memory The programmer’s model.text,.data –user program (instruction memory) and data area.ktext,.kdata –kernel program and.
Datorteknik OperatingSystem bild 1 the Operating System (OS)
MIPS Assembly Language CPSC 321 Computer Architecture Andreas Klappenecker.
Fall EE 333 Lillevik480f05-a2 University of Portland School of Engineering EE 333 Exam 2 November 10, 2005 Instructions 1.Print your name, student.
Some Samples of MIPS Assembly Language Lecture for CPSC 5155 Edward Bosworth, Ph.D. Computer Science Department Columbus State University.
Input and Output CS 215 Lecture #20.
MIPS Pipelined Datapath
1 Recap (Pipelining). 2 What is Pipelining? A way of speeding up execution of tasks Key idea : overlap execution of multiple taks.
CSCE 212 Quiz 9 – 3/30/11 1.What is the clock cycle time based on for single-cycle and for pipelining? 2.What two actions can be done to resolve data hazards?
1 COMP541 Completing the MIPS Datapath Montek Singh Mar 27, 2007.
What are Exception and Interrupts? MIPS terminology Exception: any unexpected change in the internal control flow – Invoking an operating system service.
CSCI-365 Computer Organization Lecture Note: Some slides and/or pictures in the following are adapted from: Computer Organization and Design, Patterson.
Input and Output Computer Organization and Assembly Language: Module 9.
VAX. Agenda VAX and its History VAX ISA VAX Virtual Address Microcode.
1 COMP541 Final Missing Pieces of MIPS: Adding Memory & I/O Montek Singh Apr 11, 2012.
1 COMP541 Multicycle MIPS Montek Singh Apr 4, 2012.
Sample Code (Simple) Run the following code on a pipelined datapath: add1 2 3 ; reg 3 = reg 1 + reg 2 nand ; reg 6 = reg 4 & reg 5 lw ; reg.
Computer Architecture CSE 3322 Lecture 3 Assignment: 2.4.1, 2.4.4, 2.6.1, , Due 2/3/09 Read 2.8.
ECE 353 Lab 2 Pipeline Simulator. Aims Further experience in C programming Handling strings Further experience in the use of assertions Reinforce concepts.
COMP541 Multicycle MIPS Montek Singh Mar 25, 2010.
CSE431 L06 Basic MIPS Pipelining.1Irwin, PSU, 2005 MIPS Pipeline Datapath Modifications  What do we need to add/modify in our MIPS datapath? l State registers.
MIPS Processor.
Simulator Outline of MIPS Simulator project  Write a simulator for the MIPS five-stage pipeline that does the following: Implements a subset of.
STUDY OF PIC MICROCONTROLLERS.. Design Flow C CODE Hex File Assembly Code Compiler Assembler Chip Programming.
Computer System Structures
Homework Reading Tokheim, Chapter 12-1 through 12-4.
Lecture 11 Virtual Memory
Interrupts and exceptions
Memory The programmer’s model .text, .data .ktext, .kdata
Handling Exceptions In MIPS, exceptions managed by a System Control Coprocessor (CP0) Save PC of offending (or interrupted) instruction In MIPS: Exception.
CS2100 Computer Organization
Operating Systems CMPSC 473
MIPS I/O and Interrupt.
Virtual Memory User memory model so far:
CSCI206 - Computer Organization & Programming
the Operating System (OS)
ELEN 468 Advanced Logic Design
Input/Output Interface
Input/Output.
Extensions to the Multicycle CPU
Single Clock Datapath With Control
Buses.
ECE 353 Lab 3 Pipeline Simulator
Principles of Computers 16th Lecture
MIPS I/O and Interrupt.
Data Representation – Instructions
CSCI206 - Computer Organization & Programming
Intel
CS/COE0447 Computer Organization & Assembly Language
CSCI206 - Computer Organization & Programming
Instruction cycle Instruction: A command given to the microprocessor to perform an operation Program : A set of instructions given in a sequential.
Paging Lecture November 2018.
CSCI206 - Computer Organization & Programming
MIPS assembly.
CSCI206 - Computer Organization & Programming
Systems Architecture II
Intel 8080 Processor The 8080 was an 8-bit processor
CSCI206 - Computer Organization & Programming
Principles of Computers 20th Lecture
Chapter 4: Representing instructions
COMP541 Datapaths I Montek Singh Mar 18, 2010.
Chapter 4 Introduction to Computer Organization
MIPS I/O and Interrupt.
Computer System Structures
Computer Architecture
MIPS Pipelined Datapath
A CCESSING I/O DEVICES. I/O devices accessed through I/O interface. Requirements for I/O interface: –CPU communication –Device communication –Data buffering.
MIPS Assembly.
Presentation transcript:

Memory The programmer’s model .text, .data .ktext, .kdata user program (instruction memory) and data area .ktext, .kdata kernel program and data area The computer’s model instruction memory user space 0-7fffffff, kernel space 80000000 - ffffffff data memory

How can we tell User/Kernel apart? 31 30 29 28 27 ? x x x x…... By looking at the address! PC[31] 0, User program 1, Kernel program data addr[31] 0, User data 1, Kernel data

Address Decoding So far; Instruction decoding Now address decoding 32 PC PC[31] TAP BOX [31]

How to detect a kernel instruction CPU model How to detect a kernel instruction kinst CP0 MIPS PIPELINE 32 instruction address [31] Instruction Memory

How to detect kernel data access CPU model How to detect kernel data access kdata CP0 MIPS PIPELINE data mem address 32 [31] Instruction Memory

Address Mapping CP0 MIPS PIPELINE data mem address 32 32 data 8/16/32 bits Address bus Data bus

Address Mapping CP0 MIPS PIPELINE Control signals r/w, 8, 16, 32 bits Address bus Data bus Control bus

Address Mapping Address bus Data bus Control bus 00……0 .. . 0fff…..f 10……0 .. . 1fff…..f n0……0 .. . nfff…..f …. Mem 1 Mem 2 Mem n

Enable and REDUCED address Address 0-7fffffff 31 30 29 28 27 [27:0] points out the REDUCED address in mem 1 mem 1 Enable

lw $t0 0($t1), $t1=0…0 Address bus Data bus Control bus read=(ADDR[31..28]=0000) and CTRL[READ] word=CTRL[WORD] 32 address decoder read, word 28 data word 00……0 .. . 0fff…..f

lw $t0 0($t1), $t1=0…0 Address bus Data bus Control bus CTRL[stall]=0 Until data ready 32 address decoder read, word 28 data word 00……0 .. . 0fff…..f

sb $t0 0($t1), $t1=0…0 Address bus Data bus Control bus write=(ADDR[31..28]=0000) and CTRL[WRITE] byte=CTRL[BYTE] 32 address decoder write, byte 28 data word 00……0 .. . 0fff…..f

sw $t0 0($t1), $t1=0…1 Address bus Data bus Control bus CTRL[ALIGNMENT]=(ADDR[31..28]=0000) and (ADDR[0] or ADDR[1]) 32 address decoder Alignment Error!!!