VLSI design Short channel Effects in Deep Submicron CMOS UNIT II : BASIC ELECTRICAL PROPERTIES Sreenivasa Rao CH Department of Electronics and Communication Engineering VNR Vignana Jyothi Institute of Engineering and Technology Hyderabad-500090 Email: sreenivasarao_ch@vnrvjiet.in Web: http://www.vnrvjiet.ac.in/vlsidesign/ 27/01/2009 VLSI design VLSI design

Short channel Effects in Deep Submicron CMOS VLSI design

CMOS Scaling Defines as reduction of the dimension of different parameters of MOSFET . Why Scaling ?? Increase device packing density. Improve speed or frequency response (1/L) Improve current drive (Transconductance Gm ) Decrease Power consumption VLSI design

Types of Scaling Constant field scaling – Requires to reduce power supply voltage with the reduction of feature size . Constant voltage scaling – Provides voltage compatibility with older circuit technologies . Increasing electric field leads to velocity saturation , mobility degradation , sub threshold leakage VLSI design

Reliability Device failure/degradation Accelerated life testing Hot electron effect Electromigration Oxide failure Transistor degradation Accelerated life testing Over-voltage, over-temperature VLSI design

Limiting Factors of CMOS scaling Punch Through Drain Induced Barrier Lowering (DIBL) Hot Carrier Effect VLSI design

Hot-Carrier Effects threshold voltages can drift over time ⇒ long-term reliability problem electrons with high velocity (with an electrical field of at least 104 V/cm) can leave the silicon and tunnel into the gate oxide, where they are trapped ⇒ increasing the VT of NMOS, decreasing the VT of PMOS VLSI design

Hot Carrier Effects Supply voltages dropping slower than channel length – as a result electric fields in channel continue to increase. • High fields in the channel produce hot carrier effect – charge carriers in channel accelerated by high E-field – accelerated carriers start colliding with the substrate atoms • generates electron-hole pairs during the collision • these will be accelerated, collide with substrate atoms and form even more electron-hole pairs: called impact ionization VLSI design

– impact ionization can lead to • avalanche breakdown within the device • large substrate currents • degradation of the oxide – high energy electrons collide with gate oxide and become imbedded in the oxide – cause a shift in threshold voltage – considered catastrophic effect, leads to unstable performance VLSI design

• Hot carrier effect must be considered for submicron devices – may potentially be a limiting factor in how far devices can be scaled down • unless we can reduce electric fields in channel • To reduce hot carrier effects, increase channel length • pMOS devices may be better overall for deep submicron circuits – hole mobility is closer to electron mobility under high electric fields which occur in submicron devices – hot carrier effects are worse in nMOS devices than pMOS VLSI design

Hot Carrier Effect As feature size decreases , Electric field in channel region increases which leads to gain high kinetic energy by holes & electron (Hot carrier) . High kinetic energy helps them to inject inside gate oxide and form interface states , which in turns causes degradation of circuit performance . This effect is called Hot Carrier Effect . VLSI design

Cause of Hot Carrier Effect In submicron device , channel doping is increased to reduce the channel depletion region . High doping increases threshold voltage . Gate oxide thickness reduces to control the threshold voltage . Due to channeling doping concentration , decreased channel length & reduced gate oxide thickness , hot carrier generated & injected to gate oxide. VLSI design

Hot Electron Injection When both VG & VD very higher than source voltage , some electrons driven towards gate oxide . VLSI design

Suppression of Hot Carrier Effect Reduction of Hot-Carrier Generation Reduce the high drain field Reduction Hot Carrier Trapping Use High quality gate oxide Reduce bond breakage rate during hot carrier injection VLSI design

floating-gate transistor VLSI design

Threshold Variations VT0 = f(manufacturing technology, VSB, L, W, VDS) decreases with L for short-channel devices decreases with increasing VDS (drain-induced barrier lowering, DIBL) ⇒ For high enough values of the drain voltage, the source and drain region can be shorted together. (punch-through) VLSI design

punch through High enough values values of the drain voltage, the Source and Drain regions can even shorted together. Drain current no longer controlled by gate Drain current does not saturate Huge sub-threshold currents Transistors won’t “turn off” Punch through defines an upper bound on drain-source voltage that can be applied over the transistor L ++VD xo S&D depletions touch – punch through rj rj Ws e- WD VLSI design

Threshold Variations Threshold as a function of the length (for low VDS) Drain-induced barrier lowering (for low L) …(DIBL) V T Low DS threshold VDS L Long-channel threshold VLSI design

DRAIN INDUCED BARRIER LOWERING (DIBL) Drain induced barrier lowering (DIBL) is threshold voltage reduction with drain voltage Drain current is influenced by drain voltage not just gate voltage Raising the Drain –Source (Bulk) voltage ,increases the width of the Drain –Junction depletion region.Threshold decreases with increasing Vds. VG VD n n Barrier Lowering p VLSI design

Drain Induced BL (DIBL) S D S D Barrier height Barrier height Increase Drain voltage Increase Drain voltage Long L Short L VDS  VT IOFF  VLSI design

DIBL effects : DIBL effects : VDS VTHN IDS,Subth PLEAK VLSI design

Threshold Voltage Rolloff/DIBL VLSI design

Leff VTHN IDS,Subth PLEAK Short Channel Effects N+ L [um] VTH [V] 0.1 0.2 0.3 0.4 Short-channel effects : Leff VTHN IDS,Subth PLEAK VLSI design

THRESHOLD VOLTAGE VARIATIONS VT variations Oxide thickness Short channel effects: DIBL Channel length variations Doping density fluctuations Oxide charge variations (minimal) Gate doping density/depletion Boron penetration into substrate VLSI design

WHAT DO WE DO? We require continued Cox increase to maintain drive current, but tox is limited reduce tox or increase Kox Or increase Kox and tox The gain in oxide leakage current is substantial VLSI design

References CMOS VLSI design, Neil H.E.Weste,David Harris,Ayan Banerjee Digital Integrated Circuits - John M. Rabaey, PHI VLSI design

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