Low Power cmos and Adiabatic Circuits Presented by Tarek Mahmoud Samy My presentation today is titled, “Low Power cmos and Adiabatic Circuits.”

Outline Introduction The Adiabatic-Charging Principle Implementation Issues Adiabatic Logic Adiabatic Power Supplies Conclusion References So I am going to begin with introduction. Then, I’m going to briefly talk about The Adiabatic-Charging Principle. Then This will be followed with the Implementation Issues of the Adiabatic Logic Adiabatic Power Supplies finally I will end by presenting conclusions.

Introduction Why low power? Desirability of portable devices. Advent of hand held battery operated devices. Large power dissipation requires larger heat sinks hence increased area. Cost of providing power has resulted in significant interest in power reduction of non portable devices Why low power? It is Desirable in the portable devices. Advent of hand held battery operated devices. even in the non prtable devices or battery operated devices Large power dissipation requires larger heat sinks hence increased area. And Cost of providing power has resulted in significant interest in power reduction of non portable devices

Introduction In 2001 It was Predicted that “Ten years from now, microprocessors will run at 10GHz to 30GHz and be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .” In 2001 It was Predicted that “Ten years from now, microprocessors will run at 10GHz to 30GHz and will be capable of processing 1 trillion operations per second – about the same number of calculations that the world's fastest supercomputer can perform now. “Unfortunately, if nothing changes these chips will produce as much heat, for their proportional size, as a nuclear reactor. . . .” Patrick P. Gelsinger Senior Vice PresidentGeneral Manager Digital Enterprise Group INTEL CORP

Components of Power Dynamic Static Signal transitions Short-circuit Logic activity Glitches Short-circuit Static Leakage The Dissipation of Power in the cmos circuits can be categorized into: Dynamic Power which is Dissipated in: Signal transitions Logic activity Glitches Short-circuit And Static Power which is Dissipated in Leakage

Power Dissipation in CMOS Logic (0.25µ) Ptotal (0→1) = CL VDD2 + tscVDD Ipeak + VDDleakage This fig shows the percentage of the Dissipation in a cmos inverter And we can see that P -switching is the largest one , So we are going to focus on finding a way that we are not just charging the capacitor and then discharge it But we will find a way to return its charge to the supply to be reused later So we are moving to adiabatic circuits CL %75 %20 %5

The Adiabatic-Charging Principle

The Adiabatic-Charging Principle When the input, Vin is pulled low the pMOS device turns on and the linear load capacitance (C) is charged from 0 to V The energy dissipation is Which is the energy Ecap which is stored on C after charging, is also When the input, Vin is pulled low, pMOS device turns on and the linear load capacitance (C) is charged from 0 to V 1)The charging process causes energy dissipation in the pMOS device, because the charge experiences a potential drop on its way from the supply node to the load. Now the energy dissipation is equal the average potential drop traversed (Vavg) which equals V/2 multiplied by the charge stored in the capacitor which equals C multiplied by V And we can find that the ENERGY DISSIPATION EQUALS the energy stored in the capacitor after charging

The Adiabatic-Charging Principle It is clear from the expression for The energy dissipation equation that dissipation is reduced if V or C are made smaller. But it seems that nothing can be done if both C and V are fixed Because: Reduction of V without correspondingly reducing Vt reduces speed severely and V must be at least 2Vt. Reduction in physical capacitance by reducing sizes of devices reduces driving capability hence speed

The Adiabatic-Charging Principle However the dissipation would be reduced if The (Vavg) could somehow be reduced below V/2

The Adiabatic-Charging Principle Consider now the idealized resistive switch network the voltage drop across the switch is IR throughout the charging, so the energy dissipation is In this circuit The constant supply voltage level, V, has been replaced by a constant current source, I now Consider the resistive switch network the voltage drop across the switch is IR throughout the charging, so the energy dissipation is =IR*CV

The Adiabatic-Charging Principle CMOS implementation of the Previous circuit. This one is the same circuit but The switch and the resistance R are implemented as a transmission gate. 12

The Adiabatic-Charging Principle The charging current I is equal to CV/T When this expression is substituted for I the result is the expression The charging current I is equal to CV/T where T is the charging time used to charge C from 0 to V And by substituting for is We have the equation that energy of current dissipated equals RC/T *CV^2 13

The Adiabatic-Charging Principle We may now make several observations Ecurr can be lower than Econv if T is long enough. A lower path resistance R brings a lower dissipation If the current direction is reversed, C is discharged through the same path through which it was charged. now we can observe that energy of the dissipated current can become lower than that dissipated from the constant voltage source if the T is long enough Or by decreasing the resistance If the current direction is reversed, C is discharged through the same path through which it was charged. 14

Implementation Issues

Implementation Issues The constant-current generator presents implementation problems. It is not clear how to build individual controllable constant-current generators for each capacitive load in a large circuit without wasting more power than was gained by introducing them. Thus, all adiabatic-charging circuits presented to date use A time-dependent voltage source that generates periodic positive- and negative linear voltage ramps which creates current waveforms similar to those generated by the current source

Adiabatic Logic

Adiabatic Logic This figure is the same of the previous figure but adds a clamp device to ensure that the output is securely grounded when it is not to be charged This figure is the same of the previous figure but adds a clamp device to ensure that the output is securely grounded when it is not to be charged The transmission gate used to connect the load to the Adiabatic power supplies requires a dual-rail control signal, as do all logic gates based on transmission gates. It is not acceptable to introduce a conventional inverter to derive one of these control signals from the other. At each transition, the inverter would dissipate energy, which would not scale with the transition time, as required for fully adiabatic operation. 18

Adiabatic Logic An adiabatic logic gate is “almost” the same as a standard logic gate. Generates both and Input must stay stable for the entire HIGH period of the ramp power clock Logic evaluates once per cycle (of the ramp power clock) “Similar to Domino differential outputs” An adiabatic logic gate is “almost” the same as a standard logic gate And this circuits should generate both the output and its invert Also the adiabatic logic circuits its inputs should stay stable for the “high” period of the ramp clock power The evaluation happens once per cycle (of the ramp power clock) “Similar to Domino differential circuits” 19

Adiabatic Logic There is a problem if we need to make sure input stay stable for the charge recovery. Option #1: Power (clock) for each stage must be slightly different. Option #2: latch the data between several stages. Option #3: Consider every gate to have separate charge and discharge paths. so out problem now in to make sure that inputs will stay un changed To solve this problem some techniques are being used Such as Using diffrant power clocks for each stage Or by latching the data between stages Or to Consider every gate to have separate charge and discharge paths. 20

Option #1: Power (clock) for each stage must be slightly different. Longer for the earlier stage. Otherwise, charge is not recycled. In this technique Power (clock) for each stage will be slightly different It means that the power pulse will be applied to the first block until the last one gives its output and so on Otherwise, charge is not recycled 21

Option #2: Data stays constant latch the data between several stages But that will Waste power for latching (which is not friendly) So Adiabatic latch whould be used An other technique is to latch the data between several stages and Data stays constant But that will Waste power for latching (which is not friendly) Which is two-phase, nonoverlapping clocks. The input value is latched on the falling edge of phase 1 and buffered through the inverter pair. When the latched value is low, the clamp device holds the output at ground potential, and the transmission gate devices are turned off. When the latched value is high, the transmission gate connects the load to V2 in time for the phase-2 clock pulse. 22

Option #3: Consider every gate to have separate charge and discharge paths The last technique is to Consider every gate to have separate paths of charging and discharging So that inputs for charging does not need to stay asserted. F is charging G is discharging So that inputs for charging does not need to stay asserted. F is charging G is discharging 23

Option #3: The capacitance C is charged though one path A. later discharged through another path B. The inputs to the path A must be stable throughout the charging. And inputs to path B must be stable throughout the discharging. The capacitance C is charged though one path A. later discharged through another path B. The inputs to the path A must be stable throughout the charging. And inputs to path B must be stable throughout the discharging. The inputs must now be held static throughout the charging of the load, while the later discharge is controlled by another set of signals. 24

Option #3: The solution is more complex: each stage in a fully adiabatic pipeline must generate: signals that control the charging path of the following stage signals that control the discharging path of the previous stage in the pipeline. Now to have the two paths The solution is going to be more complex For a fully adiabatic pipeline our design should generate signals that control the charging path of the following stage And signals that control the discharging path of the previous stage in the pipeline. 25

Option #3: Node capacitances in this reversible pipeline are charged and discharged through two different paths. Each discharge path implements the inverse logic function to the charge path of the next pipeline stage. Thus, the discharge path has full information of the state of the variables to erase. To make this approach workable, all combinational functions used in the pipeline must be invertible: there must exist an inverse function, which can compute the inputs to the original function from its results. The resulting pipeline is reversible and runs backward if the clocks are reversed in time. This reversibility property is characteristic of all fully adiabatic pipelines. 26

Reversible XOR Example: Example: XOR Forward F = A xor B F_b = A xnor B Reverse Discharge A A = F xor B B = F_b xnor A Need to buffer A and B for reversibility. Reversibility is a property of logic. It has been proven to be possible widely but has significant overhead. 27

Some adiabatic logic Implementation

Some adiabatic logic Implementations adiabatic logic circuits are Similar logic family as Differential Cascode Voltage Switch Logic (or DCVSL) Except Power is Clocked adiabatic logic circuits are Similar logic family as Differential Cascode Voltage Switch Logic (or DCVSL) Except Power is Clocked 29

Some adiabatic logic Implementations Timing diagram for 2N-2P family Here we introduce some adiabatic logic circuits doing logic functions Here we can find the adiabatic inverter/buffer implemented by 2N-2P family 2N-2P Inverter 30

Some adiabatic logic Implementations 2N-2N2P logic family inverter/buffer And here an other circuit of the same function inverter/buffer but implemented with 2N-2N2P logic family 31

Some adiabatic logic Implementations 2N-2N2P logic family Complex gate And here a complex gate using the same techneque of the last one 32

Example of adiabatic AND/NAND gate The figure presents an AND/NAND gate. When the clock signal rises, the right output will be held low if both inputs are high the output not held low will follow the clock signal and be charged adiabatically once the corresponding pMOS device has turned on. The change from one stable state to the other state occurs And this is an example of and/nand gate implemented as adiabatic circuit 33

Some adiabatic logic Implementations Pass-transistor Adiabatic Logic (PAL) Uses one clock pulse source instead of the VDD and the ground More fully adiabatic than previous. But Slower But Slower Pass-transistor Adiabatic Logic (PAL) This circuit Uses one clock pulse source instead of the VDD and the ground Its advantage is that it is fully adiabatic than previous circuits fully adiabatic than previous 34

Some adiabatic logic Implementations (CAL) Clocked Adiabatic Logic Using a single PC With additional signal CX enables NMOS logic tree to perform switching Clocked Adiabatic Logic this circuit uses power clock pluses instead of the VDD only And uses additional signal CX enables NMOS logic tree to perform switching The two n mos of fo and f0\ can be replaced to implement any other logic function 35

Adiabatic Charge Pump

Adiabatic Charge Pump Three-input stage charge pump.

Adiabatic Power Supplies

Adiabatic Power Supplies Adiabatic switching can reduce overall power dissipation only if some part of the switching-circuit node energies can be recovered and reused. the recovered node energies must somehow be stored in the Adiabatic power supplies while waiting to be reused. Adiabatic switching can reduce overall power dissipation only if some part of the switching-circuit node energies can be recovered and reused. the recovered node energies must somehow be stored in the Adiabatic power supplies while waiting to be reused. The main energy-storing elements in the power supplies circuit are inductors and capacitors. 39

LC resonance circuit Using LC resonator to generate the sine wave. Capacitance is really the load capacitance. Once the circuit has been excited the energy will oscillate between the inductance and the capacitance, with a frequency proportional to the inverse of the square root of the LC product. A continued near-sinusoidal waveform may be produced if the energy is reloaded regularly Now the target of the adiabatic power supply is to generate power clock pulses to operate the adiabatic circuits And these clocks are generated by LC resonator Which is generating sine wave. The Capacitance is really the load capacitance. Once the circuit has been excited the energy will oscillate between the inductance and the capacitance, with a frequency proportional to the inverse of the square root of the LC product. 40

LC resonance circuit The logic circuit, in the dashed box, is represented as an RC link, where the C corresponds to the node capacitances and the R corresponds to the on-resistances of the logic gates. The RC link is periodically shunted by the nMOS device. When the control signal frequency agrees with the LC resonance, the voltage across the RC link approximates a sine wave with a peak-to-peak value of V. 41

LC resonance circuit the frequency of operation is set by the total driven capacitance C and the resonance inductor L. It may be possible to operate the Adiabatic power supplies at a frequency slightly different from its self-resonance frequency, but at a reduced efficiency. 42

resonance circuit The Adiabatic power supplies designs described previously use inductors for energy storage. Inductors have several practical drawbacks: large inductors cannot be integrated on silicon chips. timing errors can cause ringing or damaging voltage spikes. the inductor-based Adiabatic power supplies solutions suffer from jitter when subjected to variable capacitive loads. It is possible to avoid these drawbacks by using capacitors for energy storage 43

resonance circuit An alternate way to think of adiabatic switching is to consider the charging to occur over many steps. An alternate way to think of adiabatic switching is to consider the charging to occur over many steps. And each step is VDD/n which is the number of the steps Which is controlled using n number of switchs each inputs value of vdd/n which is incremented up to vdd 44

resonance circuit A stepwise driver for the load capacitance CL. The load is connected to each of the large “tank” capacitors, CTi.in sequence during charging, and in reverse sequence during discharging. The tank capacitor voltages converge to I(V/N). So this design can be applied using n number of transistors each connected to large “tank” capacitors, CTi And by sequence transistors are opening to make the charging, and in reverse sequence during discharging. To make the pulse shape 45

rotary traveling-wave oscillator Researchers have therefore looked to alternative oscillator mechanisms for better phase stability and lower power consumption. Previous adiabatic LC resonant clocks provided only a sinusoidal or semi-sinusoidal clock, making fast edge rates difficult to achieve. 46

rotary traveling-wave oscillator John Wood introduced the rotary traveling-wave oscillator (RTWO) RTWO is a differential LC transmission-line oscillator which produces gigahertz-rate multiphase (360 ) square waves with low jitter 47

CONCEPT OF THE ROTARY CLOCK OSCILLATOR This figure shows an open loop of differential transmission line (demonstrate LC characteristics) connected to a battery through an ideal switch. When the switch is closed, a voltage wave begins to travel counterclockwise around the loop 48

CONCEPT OF THE ROTARY CLOCK OSCILLATOR This Figure shows a similar loop, with the voltage source replaced by a cross-connection of the inner and outer conductors to cause a signal inversion signal inversion. If there were no losses, a wave could travel on this ring for providing a full clock cycle every rotation of the ring 49

CONCEPT OF THE ROTARY CLOCK OSCILLATOR In real applications, multiple antiparallel inverter pairs are added to the line to overcome losses The oscillation frequency is expressed as: where LT is the total inductance of the line and CT is the total capacitance. 50

Conclusions

Conclusions adiabatic Logic designs will become an absolute requirement for most high-performance computing over the course of the next few decades. To achieve this, transistor rules must be followed, and an increasing degree of logical reversibility (with efficient designs) will be required. Some examples of truly-adiabatic design styles were presented, and a general, efficient adiabatic CMOS design methodology is under development. 52

References Low-Power CMOS Circuits,Technology, Logic Design and CAD Tools,Christian Piguet. A 18GHz Rotary Traveling Wave VCO in CMOS with I/Q outputs, G. Le Grand de Mercey. low-power digital system based on adiabatic-switching principles,william c.athas. Rotary Traveling-Wave Oscillator Arrays:A New Clock Technology,John Wood. 53