Data Aquisition System Front-end module DAQ board 1 ADC LOGIC DATA REDUCTION LOGIC SER DESER PROCESSOR MODULE Ethernet 32 channels 1 ADC DESER SER Preamplifier modules serial links clock module one for all DAQ boards 6.06.2006 Max Hess

electrically isolated Front-end module MUX: 32 ADC channels + 1 channel for status 1 ADC SHIFT REG 12 REG 12 MUX CODER: create DC-balanced signal code ( 3x 4B5B-code) DS92LV16 32 channels 12 16 CODER SERIALIZER 1 12 12 ADC SHIFT REG REG to DAQ (12) 720 Mb/s CONTROL LOGIC CS* (16) DE-SERIALIZER sclk rclk : 2 from DAQ FPGA Altera EP1C3T144C8 Development LOGIC CS*: ADC conversion start (1MS/s) sclk: sample clock = 20 MHz rclk: Readout clock = 40 MHz Linear regulators DC-DC converters Preamplifier modules interchangeable for LArDM, ArgonTube, etc. 24VDC input electrically isolated 26.06.2006 Max Hess

Front-end module 2 amplifier / print input connector ADC‘s for 32 channels (68 pole flat cable) 2 amplifier / print ADC‘s Analog Devices ADC121S101 FPGA Altera EP1C3T144C8 100 mm Serializer/Deserializer NS DS92LV16 connection to DAQ board (serial link) 26.06.2006 Max Hess

Front-end box 7 or 8 Front-End modules = 224 or 256 channels / box input connectors for 32 channels (68 pole flat cable) 3 HE = 133 mm 26.06.2006 Max Hess

Front-end box Ethernet connectors 26.06.2006 Max Hess

Data Aquisition board INPUT MEMORY Processor core with FLASH MEMORY SDRAM Ethernet Interface MULTI-CHIP MODULE AXIS ETRAX 100LX DS92LV16 16 16 DE-SERIALIZER INPUT FIFO 16 OUTPUT FIFO Ethernet rclk from Front-end FPGA 720 Mb/s circular buffer logic for input memory signal comparator timer for time stamp generation data reduction logic from input memory to output FIFO SERIALIZER signal detect out to Front-end ext. trigger in EXTERNAL CLOCK MODULE one for all DAQ modules timer clock CS* rclk rclk: Readout clock = 2 x ADC clock CS*: ADC conversion start slow control 26.06.2006 Max Hess

a complete Linux system on a small board ETRAX 100LX MCM 4+16 AXIS 82+ Developer Board FOX Board www.developer.axis.com www.acmesystems.it 26.06.2006 Max Hess

Schedule DM Q-amplifier layout prod test prod. 16p test 1p Front-end module scheme layout prod. 2p test FPGA programming Serial link 1. test Power print scheme layout prod 2p Front-end box constr. prod 2p DAQ board specifications scheme layout prod. test HW+SW 1p FPGA programming AXIS ETRAX order 1. test software development LAr amplifier layout prod 1p test prod. 16p ETHZ End of 2006 june 2006 LHEP 26.06.2006 Max Hess