Presented By: Rob Douglas, Alex Alexandrov Flash Memory Presented By: Rob Douglas, Alex Alexandrov

Points of Discussion Flash Memory Generalities History of Flash Memory Construction & Properties History of Flash Memory NOR & NAND Architectures Optimizations Standardization New Developments & Future of Flash Closing Statements

Flash Memory A type of EEPROM (Electrically-Erasable Programmable Read-Only Memory) Non-volatile, solid state technology Relatively limited lifespan Information is stored in an array of memory cells made from floating-gate (FG) transistors

Flash Memory Packaged inside a memory card: Extremely durable Can withstand intense pressure Immersion in water Better kinetic shock resistance than hard disks Average power requirements range from 5V-12V

Flash Memory Cell

History of Flash Memory Invented by Fujio Masuoka while he was working for Toshiba in the early 1980s First introduced at the 1984 International Electron Devices Meeting in San Francisco

Manufacturers of Flash

NOR Flash Memory Developed to replace read only memory Full address and data buses allow random access to any memory location Can access any memory cell Slow sequential access

NAND Flash Memory Developed to replace hard disks Sequential-accessed command and data registers replace the external bus of NOR Decreases chip real estate Can only access pages Faster sequential access

Optimizations Wear levelling Bad block management Counting writes & dynamically remapping blocks Bad block management Write verification and remapping bad sectors Multi-Level Cell technology Memory cells store more than one bit

Standardization Part of the reason for the success of Flash memory Open NAND Flash Interface Working Group developed standard low-level interface Standard pinout Standard command set for reading, writing, and erasing NAND flash chips Mechanism for self-identification

New Developments AND Flash DINOR (DIvided bit-line NOR) Flash Bit line replaced with embedded diffusion line to reduce cell size Low power dissipation (3V) DINOR (DIvided bit-line NOR) Flash Attempts to reduce the chip real estate compared to conventional NOR Low power dissipation (3V), sector erase, high data transfer rate

Future of Flash Memory Continues to be among the most aggressively scaled electronic technologies Memory cell size minimum of 20 nm expected to be met in 2010 May be replaced by Phase-Change RAM or other emerging technologies

In Closing… One of the most popular alternatives for portable device storage Aggressive advances are still being made

References Wikipedia - Flash Memory How Stuff Works - Flash Memory http://smithsonianchips.si.edu

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