A few notes on Altera transceivers Anton Kapliy January 2011

Transceiver datapath Circled in RED: 8b/10b encoder/decoder and CDR unit. 8b/10b is required to maintain high transition density in the received data stream. It also provides a basic error detection mechanism – see next page. Since comma always appears in LSB byte, we can also use it to establish byte order Lock byte boundary by detecting a 10-bit comma character from TLK2501

8b/10b 256 8-bit characters => 1024 10-bit characters Larger 10-bit phase space => Select mappings with {5/5,6/4,4/6} bit parity E.g, 0011001111 – 6/4, sent if “RD-” Every 6/4 or 4/6 has a complement: E.g, 1100110000 – 4/6, sent if “RD+” To maintain overall DC balance and uniform transition density, RD+ and RD- alternate Error detection: unused 10-bit code OR disparity violation.

TLK2501 synchronization TLK2501 only synchronizes on this comma In order to guarantee that K28.5 commas with correct disparity are received by TLK synchronization circuit, the first IDLE must be selected judiciously depending on running disparity. If a wrong IDLE is sent (e.g., /I2/ after RD+ or /I1/ after RD-), TLK receiver will assert error on received data.

ALTGX 8b/10b limitation 8b/10b encoder does not provide running disparity, so we can't send the correct IDLE (from one of Altera implementation guides) Altera has an 8b/10b megafunction that support 16b/20b cascading, but it is not free

8b/10b logic implementation 8b/10b map is usually implemented as a complex network of gates. This was the subject of a 1984 patent from IBM. 16b/20b implementation is the subject of more recent patents (2007) A simpler option is a MRAM-based lookup table for the entire mapping. But this would take up ~10% of Cyclone IV resources.

Alternative lookup-based solution ALTGX provides optional interface to force running disparity to an arbitrary value data[8] Flip LUT (MRAM) Tells whether the encoded version of this 8bit word would flip running disparity disparity_flipped clk Given 16-bit data from LSC core, the upper and lower 8 bits are simultaneously sent to two flip LUTs. One clock later, we receive corresponding disparity_flipped bits. Together with running disparity in the end of last 16-bit data block, they tell us: Disparity encoding for upper and lowe 8 bits of current word Running disparity in the end of transmission of current 16-bit word

Transceiver reset sequence Transmission is easy: just need PLL to lock Reception is more complicated. In the end, we wait for CDR's to lock

Operation with missing FTK link? Prevent LSC initialization / operation if FTK receive line is missing Have a switch on the board to choose whether we allow FTK-less operation or not Have a separate version of firmware for operation with/without FTK Have a ~millisecond delay to see if FTK receiver CDR is locked; if not – continue operation without FTK.