FPGA IRRADIATION and TESTING PLANS (Update) Ray Mountain, Marina Artuso, Bin Gui Syracuse University OUTLINE: Design Flow Peripherals / Communications PLL / Memory Testing Scheme Summary

“DESIGN FLOW” of PROJECT First stage: Concentrate on internal/core workings of A3PE1500 Understanding basic core behavior of FPGA Using VHDL to configure logic cells, clocks, shift registers, etc. Understand structure and use of RAM-blocks/Flash-ROM Understand configuration and programming procedure Second stage: Concentrate on “peripheral” connections LVDS I/O ports and external (off-board) connections JTAG interface details CLK inputs, PLL operation LabVIEW interface and control (*) Third stage: Concentrate on testing procedure Develop, test, and refine SEE algorithms Bench test testing sequence and do timing studies Last stage: Irradiation Tests Packaging FPGA for tests Schedule and irradiate FPGA (start with protons) Identify failure modes, mitigation schemes Plus: Modify and iterate Faster communication, refine tests Different species (n, g) done here R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -2-

PERIPHERAL CONNECTIONS Main: PC (IP) → Router (LAN) → TNG (DIO) → XBD (TTL/LVDS) → (long cat5) → FPGA Plus (separately): PC (USB) → FlashPro3 (JTAG) → FPGA Router TNG-5 FPGA eval bd FlashPro3 Last time just had the scheme and programming capability… XBD (proto) WORKS! PC R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -3-

COMMUNICATIONS Elements: Issues: LabVIEW control VI Control State Machine in FPGA Lightweight comm protocol byte commands, plus enable 2-line I, 2-line O (data+ctrl) Issues: Basically works, being refined As implemented, it is slow Series of speed tests LabVIEW+IP limited < 1 kHz Not fast enough to do bitstreaming for SEU Requires workaround: on-FPGA calcs when run SEU test, similar to the config verification scheme Do-able but not very happy with this, as it is susceptible to SEE Looking into faster comm General purpose NI PXI-based, with I/O speeds up to 400 MHz Local mods: TNG uC can go to 8 MHz max, XBD to 100 MHz LabVIEW GUI Command Response AA STATUS? AB OK BA Start SEU Test AE Don’t Understand BD Send Result AC BUSY … DA DATA Control FSM R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -4-

PLL OPERATION Had some difficulties in implementing PLL Not good help from Actel on this Thanks to Albert for sample code, plus tip that there needs to be separate power to the PLLs on the eval board. We are going on this now We can now modify the frequency of clock up to 350MHz Incorporating PLL as variable clock in SEU Test Next: Establish baseline error rates on bench for speeds up to 350 MHz (or as high as we can go) Can also add dedicated PLL test on request 40 MHz (on-board oscillator) Amplitude is somewhat distorted by LVDS breakout probe but frequencies are good. 200 MHz (PLL) 350 MHz (PLL) R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -5-

MEMORY TESTS Working on this part… Plan to include triple-voting tests up to 160 MHz Store same number in three separate registers, read each one Store number in a register, read three separate times Received code from Christophe Beigbeider and Jacques using FIFO (derandomizer) with triple voting scheme Thanks! Converting from verilog and testing Testing and incorporating into control sequence In the queue… R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -6-

TESTING SCHEME v2 Outline of irradiation testing procedure: Run SEU Test algorithm (almost continuously). Cycle through different clock frequencies, up to 300 MHz using PLL. Intersperse memory checks: dynamic registers (RAM-blocks), R/W cycles, triple voting static registers (Flash-ROM), R only from core, W with JTAG if needed Periodically check configuration for corruption (i.e., verify configuration and programmability of device). load and verify config file (ours or complex one) do this without beam on target (due to large current draw during cfg) Periodically cycle power on FPGA (less frequently) Plus: refine when understand timing better, global issues (reset lines), and dedicated tests (PLLs), as requested in survey R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -7-

SUMMARY Progressing on “Design Flow” Schedule: Have basic programming and chip operation in hand Establishing hw communications link and command protocols Integrating SEU test etc. with control SM in FPGA, and PLL for different speeds Add and test memory checks Continuing to “work the problem”… Schedule: Plan to do first irradiation (protons) in April timeframe, probably at IUCF, irradiation to ~50 kRad. Will make a schedule, when we progress a bit more R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -8-

BACKUPS R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -9-

SEU TEST (1) Enter data, clock through “all” logic cells, compare at output. Use bitstream, random or pattern. Run for different clockings up to 40 MHz to check for frequency dependence This has been implemented and tested (on board, lower speeds) (offboard) Clock/Data 512-bit Shift Register 512-bit Shift Register LVDS I/O …. Target area for beam 512-bit Shift Register 512-bit Shift Register (may be onboard) Comparator Counter 512-bit Shift Register 512-bit Shift Register 512-bit Shift Register (offboard) FPGA (~38 shift registers) R. Mountain, Syracuse University Irradiation Testing of FPGAs for the LHCb Upgrade, 11 Feb 2010 -10-