The Hardware / Software Tradeoff -John Burnette- Partitioning The Hardware / Software Tradeoff -John Burnette-

Systems Requiring Codesign ASIPs synthesis (Application Specific Instruction-set Processor) Custom computing machines, for execution acceleration System on a chip (ASICs with embedded processor) Embedded systems design

Goal of Partitioning Task Obvious: find implementation that meets specifications at minimal cost Q: How was it done originally? A: Developers had to make decisions based on their design experience and expertise. Q: How can the partitioning task be automated? A: Lots of crazy math.

Varying Environments It is difficult to develop an all-encompassing partitioning technique Many different applications Many different Specifications

Varying Environments cont’d Taken from Lopez and Vallejo, “On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques”

System Model A system model must be specified. Consider: Available hardware area Available software memory size Hardware execution time Software execution time How often is task scheduled Communication time Data transfer synchronization

System Model cont’d How many coprocessors are available? How is everything connected?

Design Quality Attributes Cost and performance parameters to describe the solution. For example: What is required hardware area for co-processor? What is the design latency? What is the required memory space?

A Few Partitioning Methods Some basic partitioning methods that are considered when developing Codesign partitioning tools. Simulated Annealing Kernighan & Lin Heuristic Hierarchal Clustering Knowledge-based Partitioning

Simulated Annealing Kirpatrick, Gelatt, and Vecchi (1983) 1st Method Simulated Annealing Kirpatrick, Gelatt, and Vecchi (1983)

It’s All About the Cost Function Main goal: “to measure the quality of a solution and guide the algorithm to the best solution.” [1] Fixed costs and variable costs should be treated separately If you already have an FPGA, you might as well use it all at a fixed cost. Can’t do the same thing with an ASIC

Cost Function 1 Cost function proposed by Lopez and Vallejo: Fc( ) are corrections terms Ci is design constraint applied to i-th quality attribute of solution P and is used as a normalization parameter kci is weight factor for correction terms

Cost Function 2 Some techniques for correcting the cost function: Mean Square Error Minimization Barrier Techniques Penalty Methods

Mean Square Error Minimization Objective is to minimize the mean square error between quality attributes and their corresponding constraints. Recall FPGA example; maximum exploitation results in performance improvement with no added cost. This should be applied to goals that should be completely fulfilled instead of minimized.

Barrier Techniques Asymptotes are place in the constraint-defined boundaries => cost of any solution outside of the design space is infinity. Example of a barrier function: Ensures no hard design constraints are violated.

Penalty Methods Suitable when constraints are not too hard Do not contribute to cost function when solution is within allowable search space Solutions around border of exploration region can be accepted if really close

Penalty Methods cont’d where The weight factor Kci is most important here.

Cooling Schedule For completeness, it should be mentioned that for simulated annealing to work, a cooling schedule must be provided. This basically tunes the parameters of the optimization routine for the next execution. It would have to be done manually otherwise

Simulated Annealing cont’d Advantage: generality, can be used to optimize in many environments Disadvantage: long computation time required

Kernighan & Lin Heuristic 2nd Method Kernighan & Lin Heuristic (1970)

K&L Heuristic Based on iterative improvement Start with random initial partition Swap nodes between both sides of partition Best solution found from swap is used as new initial partition for next iteration Finishes when no more improvements are achieved

K&L Heuristic cont’d (SLIF) access graph is used to compute design quality parameters Add values of attributes associated with nodes and edges of system graph

K&L Heuristic cont’d Drawbacks Design can not be scheduled so time estimation is difficult Process involves adding node attributes => parallelism of a multiprocessor architecture is ignored.

Hierarchical Clustering 3rd Method Hierarchical Clustering

Hierarchical Clustering This method groups pairs of partitioning objects based on proximity values between these objects. Algorithm characterized by: Closeness function Cut Level in cluster tree (based on closeness)

Hierarchical Clustering cont’d Algorithm selects the two objects with best time improvement when implemented as hardware; the rest assigned to software process. Objects are gradually extracted to hardware until all constraints are met.

Hierarchical Clustering cont’d Taken from Lopez and Vallejo, “On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques” While these primary constraints are met, secondary constraints (ie, memory) can be checked before finishing

Clustering Process Control Scheme Taken from Lopez and Vallejo, “On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques”

Closeness Function This function reflects latency of information exchange between different processes. ∆ti = sti – hti represents time improvement when object i is moved from software to hardware. tcomm(vi ,vj ): communication between vi and vj. qT ,qC , qA are weight factors Closeness value is greater for objects with bigger difference between hardware and software execution time.

Closeness Function cont’d Really we want to cluster objects that meet our constraints but still use less hardware area, thus the third term. Term value is greater when the area of the resulting cluster is less than the average system area. Fourth term helps us group objects with large sized memory; this is important for consideration of memory space. After closeness is determined and clusters are formed, the hardware, software, and memory space can be determined.

Knowledge-Based Partitioning 4th Method Knowledge-Based Partitioning proposed by Lopez-Vallejo and Lopez (2003)

Knowledge-Based Partitioning Knowledge acquired by designers can be conserved as partitioning technologies become obsolete. The knowledge is included in the system. Knowledge base can be expanded as new cases are considered.

Inference Structure

Inference Structure cont’d Four inferences Match (Heuristic Classification) Assign Evaluate Select

Match Heuristic rules are stored in knowledge base to match input and output variables. Variables can be: Hardware Quite-Hardware Unkown Quite-Software Software Example: if hw-area is small and time-improvement is high and number-executions are not few then implementation is very hardware

Assign Provides first solution proposal Allocates part of the processes to hardware and some to software This step looks at system blocks, their implementation values and the system constraints (like max hardware/software area, memory available) After the “hardness” of the constraints are considered, a system configuration is composed and initial partition determined.

Evaluate After assignment, computes parameters that will characterize the design. Based on parameters we get an idea of the quality and acceptability of the design. Parameters include: Estimation of required hardware area Estimation of required memory space Execution time (latency) Communication costs (TX and penalty)

Select Purpose: revise proposed solution and search for another proposal. Two step process: Diagnosis – how close is the solution to optimum and what corrections are needed? Maybe correct to lower cost, or maybe design doesn’t meet spec yet. Operation – perform selection of new proposal based on previous info and knowledge base of prior experience.

Select Process

Knowledge-Based Partitioning cont’d Advantage: Can be used over a variety of environments. Takes advantage of system knowledge and past experience Disadvantage: Newer, so not many tools out there that do it this way.

Conclusion Main goal is to find optimized solution Minimize cost Minimize Latency Minimize power use There is no all-encompassing partitioning tool out there. Must identify your constraints and environment to choose appropriate partitioning method.

Emerging Studies Lots of attention given to partitioning methods. Verification is open for study. Currently it is hard to verify an entire HW/SW system Hard to find incompatibilities across HW/SW boundaries (usually found at prototyping stage) Codesign tools need to allow us to synthesize controls, events, response times, scheduling CoWare: http://www.coware.com/portal/page?_pageid=167,105683&_dad=cust_portal&_schema=STAGE Polis Project: http://www-cad.eecs.berkeley.edu/~polis/ ImpulseC: http://www.impulsec.com/ Lots of partitioning studies: http://www-lsi.die.upm.es/publications/publications.html

About the Math For more info on the math for the partitioning methods presented, see Lopez, J. and Vallejo, M. "On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques.“ ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003 Also online at: http://www.ee.washington.edu/class/590/peckol/doc/papers/partition1.pdf

References Lopez,J. and Vallejo, M. "On the Hardware-Software Partitioning Problem: System Modeling and Partitioning Techniques. “ACM Transactions on Design Automation of Electronic Systems, Vol. 8, No. 3, July 2003 Kirpatrick, S., Gelatt, C., Vecchi, M. “Optimization by Simulated Annealing.” Science 220, 4598, 671-680, 1983 http://www2.toki.or.id/book/AlgDesignManual/BOOK/BOOK2/NODE92.HTM http://www.queryplus.com/newsletter_2003q3.htm http://www.birc.dk/Research/expdata.html Silva, L., Sampaio, A., Barros, E. "A Constructive Approach to Hardware/Software Partitioning". Formal Methods in System Design, 24, pp. 45-90, 2004 http://www.ida.ing.tu-bs.de/research/projects/cosyma/overview/node4.html http://polimage.polito.it/~lavagno/publications/talk/same99.ppt.gz F. Balarin, E. Sentovich, M. Chiodo, P. Giusto, H. Hsieh, B. Tabbara, A. Jurecska, L. Lavagno, C. Passerone, K. Suzuki, and A. Sangiovanni-Vincentelli. “Hardware- Software Co-design of Embedded Systems -- The POLIS approach”. Kluwer Academic Publishers, 1997.

References cont’d M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, and A. Sangiovanni-Vincentelli. “Hardware/software codesign of embedded systems”. IEEE Micro, 14(4):26--36, August 1994.