Pending technical issues and plans to address and solve Outline Flux of data in the pipeline: limits and constraints, High speed serial links and connections AMChip power consumption AMChip density (number of patterns/mm^2) Density of chips in the AMBoard Function density (FPGAs) in AUX board mezzanines ROS/ROBIN configuration – bandwidth to Level-2

Flux of data in the pipeline: limits and constraints 100 kHz events: Average time available per event = 10 msec Given a 100 MHz clock: Average # words/event can transit on a link= 1000 8 Hit buses 17 bits each @100 MHz ~2 GHz serial links needed We can use a Spartan6 with 8 3-GHz GTPs 8 Road buses 36 bits each @100 MHz 3,6 GHz serial links needed We can use a Virtex6 with 8 6-GHz GTXs 2 Road Buses 16 bits @100 MHz 2 or 4 GTPs AVERAGE LIMITS per event: 1000 Hits/Hit bus → 2 buses for IBL @75 pile-up 1000 Roads/Road bus → 8000 Roads/PU Paola - FTK review 2-12-2010

To be compared with a limit of 8000 output roads. Where we are: using the variable resolution in a new AM chip Simulation includes partial implementation (use of 1 of 2 DC bits, not the best coding) Guido Volpi & Roberto Vitillo - Pisa We simulate WH events with different numbers of pile-up events Average number of roads/AMBoard bank/region AM AM w/ DC TSP 17.6 evts 5 Mpatterns 5040 959 1060 40 evts 80 Mpatterns 37000 6500 5720 75 evts 380 Mpatterns 53500 8250 5950 To be compared with a limit of 8000 output roads. The 75 pileup events exceed that limit. Indeed at that time (2021) a more powerful chip will be available

What to do next to create larger safety margins Complete use of the variable resolution AM: the simulation includes a partial implementation For Phase II (useful also for Level 1 also) Roads: push board technology to 200 MHz & exploit full bandwith of serial links. Hits: (a) increase use of serial links and use double buses for each critical layer. 3D AMchip could have an FPGA control layer and use also serial links. (b) Push board and chip technology to 200 MHz. Use 2 buses for each high occupancy layer even in the AMchip. Paola - FTK review 2-12-2010

For example for IBL: 7 Layers vs 7 buses Moreover: 3D will have an adjustable # of layers IBL @ double bandwidth. Either double internal clock, or special logic. Take the logical OR of 2 layers. Both layers store the IBL super bin. Distribute 50% data to each layer. Layer matches if any of 2 IBL layers match Special IBL layer: OR of 2 layers Internal register that feeds 8 busses Demultiplex based on MSB IBL P i x X S C T S S C C T T Input register for 7 busses Annovi, 27-09-2010

High speed serial links and connections: board frequency limits Being able to handle this serial links at the maximum speed is something we have to test directly on boards. The simulation helps easily up to 1 GHz, after that is much more complicated. We have to learn to exploit this technology at the maximum level (we have links up to 6-3 GHz, for the moment we plan to use them at half the speed). Moreover the AMBoard we have now works at 40 MHz. Pushing the Amboard performance above 100 MHz is challenging and R&D will be important. Fortunately we have time to be prepared at the very high pile-up conditions. Strategy: the initial system will be really small (8 AMBoards). If we understand that improvements are necessary we can incorporate them before building the whole system. Paola - FTK review 2-12-2010

AMChip power consumption/ AMChip density (number of patterns/mm^2) The AMchip consumption and pattern density are correlated and are critical project parameters. Our expectation is ~80kpatterns/chip and ~ 3KW for a 16 PU crate, if not: More powerful power supplies, more crates, more racks needed More powerful DC-DC converters (now 25 A @1,2 V, 48 V) w/o increasing board area occupancy (see patio in Marco talk) More problems packing tiers in 3D→ limit to # of layers. For phase I the die size of the AMchip is not critical, if the power consumption is too much we can do a smaller area final chip, but # of boards will increase For phase II it is critical, important for both L1 & L2 use. R&D will be important in this area to otpimize both pattern density and power consumption. Paola - FTK review 2-12-2010

Density of chips in the AMBoard & AUX Board The AMBoard is really full of chips: Cooling with air need to be tested. The heat is distributed on a large area. If more devices will be needed, hard to fit them Function density (FPGAs) in AUX board mezzanines: SVT boards (DO, TF) have been squeezed in single chips. Very efficient firmware is needed STRATEGY: reduce as much as possible the RAM per function request (see Spy Buffer new phylosophy in Francesco talk) If necessary more space → more diluted system → more crates and racks. Technology advancement can be exploited after demonstrator (only 8 PUs) Paola - FTK review 2-12-2010

ROS/ROBIN configuration – bandwidth to Level-2 Could the ROS/ROBIN configuration be a bottle neck for deep exploitation of FTK tracks? In particular we could want to send to outputs the track hits, the chi^2 and goodness of the track, may be more, together with the track parameters and this would increase the needed bandwidth. The limit to the average size of the whole event is now ~2,5 kB 5 helix parameters + 11 hits + chi^2/goodness = 17 words. Having 2 byte words and ~ 60 tracks per region from 75 pile-up event simulation. we get an FTK average event size of ~ 16 kB. Strategy: learn from the demonstrator. Update the system Paola - FTK review 2-12-2010

Conclusions There are a certain number of worries They can be solved. However the risk to finish with a less compact, more expensive system is not zero. Paola - FTK review 2-12-2010