Lecture 21 OUTLINE The MOSFET (cont’d) P-channel MOSFET CMOS inverter analysis Sub-threshold current Small signal model Reading: Pierret 17.3; Hu 6.7, 7.2

P-Channel MOSFET The PMOSFET turns on when VGS < VT Holes flow from SOURCE to DRAIN  DRAIN is biased at a lower potential than the SOURCE In a CMOS technology, the PMOS & NMOS threshold voltages are usually symmetric about 0, i.e. VTp = -VTn VG VDS < 0 IDS < 0 |IDS| increases with |VGS - VT| |VDS| (linear region) VS VD GATE ID P+ P+ N VB EE130/230A Fall 2013 Lecture 21, Slide 2

Long-Channel PMOSFET I-V Linear region: Saturation region: m = 1 + (3Toxe/WT) is the bulk-charge factor EE130/230A Fall 2013 Lecture 21, Slide 3

CMOS Inverter: Intuitive Perspective CIRCUIT SWITCH MODELS VDD VIN VOUT S D G VDD VDD Rp VOUT = 0V VOUT = VDD Rn Low static power consumption, since one MOSFET is always off in steady state VIN = VDD VIN = 0V EE130/230A Fall 2013 Lecture 21, Slide 4

Voltage Transfer Characteristic N: sat P: sat VOUT N: off P: lin C VDD N: sat P: lin A B D E N: lin P: sat N: lin P: off VIN VDD EE130/230A Fall 2013 Lecture 21, Slide 5

CMOS Inverter Load-Line Analysis VGSp=VIN-VDD – + VIN = VDD + VGSp – VDSp=VOUT-VDD + VOUT = VDD + VDSp IDn=-IDp increasing VIN VIN = 0 V VIN = VDD IDn=-IDp increasing VIN VOUT=VDSn VDD VDSp = 0 VDSp = - VDD EE130/230A Fall 2013 Lecture 21, Slide 6

Load-Line Analysis: Region A VGSp=VIN-VDD – + – VDSp=VOUT-VDD + IDn=-IDp VIN  VTn IDn=-IDp VOUT=VDSn VDD EE130/230A Fall 2013 Lecture 21, Slide 7

Load-Line Analysis: Region B VGSp=VIN-VDD – + – VDSp=VOUT-VDD + IDn=-IDp IDn=-IDp VDD/2 > VIN > VTn VOUT=VDSn VDD EE130/230A Fall 2013 Lecture 21, Slide 8

Load-Line Analysis: Region D VGSp=VIN-VDD – + – VDSp=VOUT-VDD + IDn=-IDp IDn=-IDp VDD – |VTp| > VIN > VDD/2 VOUT=VDSn VDD EE130/230A Fall 2013 Lecture 21, Slide 9

Load-Line Analysis: Region E VGSp=VIN-VDD – + – VDSp=VOUT-VDD + IDn=-IDp VIN > VDD – |VTp| IDn=-IDp VOUT=VDSn VDD EE130/230A Fall 2013 Lecture 21, Slide 10

MOSFET Effective Drive Current, IEFF M. H. Na et al., IEDM Technical Digest, pp. 121-124, 2002 V1 V2 V3 CMOS inverter chain: IEFF = IH + IL 2 V1 TIME VDD VDD/2 V2 V3 tpLH tpHL IDsat GND VDD S D VIN VOUT CMOS inverter: IH VIN = VDD NMOS DRAIN CURRENT IL VIN = ½VDD 0.5VDD VDD NMOS DRAIN VOLTAGE = VOUT EE130/230A Fall 2013 Lecture 21, Slide 11

Propagation Delay, td C. C. Hu, Modern Semiconductor Devices for Integrated Circuits, Fig. 6-20 VDD CMOS inverter chain: Voltage waveforms: VDD td is reduced by increasing IEFF and reducing load capacitance C EE130/230A Fall 2013 Lecture 21, Slide 12

Sub-Threshold Current For |VG| < |VT|, MOSFET current flow is limited by carrier diffusion into the channel region. The electric potential in the channel region varies linearly with VG, according to the capacitive voltage divider formula: As the potential barrier to diffusion increases linearly with decreasing VG, the diffusion current decreases exponentially: EE130/230A Fall 2013 Lecture 21, Slide 13

Sub-Threshold Swing, S log ID VGS VT Inverse slope is subthreshold swing, S [mV/dec] NMOSFET Energy Band Profile increasing E distance n(E)  exp(-E/kT) Source Drain increasing VGS EE130/230A Fall 2013 Lecture 21, Slide 14

VT Design Trade-off Low VT is desirable for high ON current: IDsat  (VDD - VT) 1 <  < 2 But high VT is needed for low OFF current: log ID Low VT VT cannot be aggressively reduced! High VT IOFF,low VT IOFF,high VT VGS EE130/230A Fall 2013 Lecture 21, Slide 15

How to minimize S? EE130/230A Fall 2013 Lecture 21, Slide 16

MOSFET Small Signal Model (Saturation Region) Conductance parameters: A small change in VG or VDS will result in a small change in ID low-frequency: high-frequency: R. F. Pierret, Semiconductor Device Fundamentals, Fig. 17.12 EE130/230A Fall 2013 Lecture 21, Slide 17

Parasitic Components EE130/230A Fall 2013 Lecture 21, Slide 18 R.S. Muller & T.I. Kamins, Device Electronics for Integrated Circuits, Fig. 8.12

MOSFET Cutoff Frequency, fT The cut-off frequency fT is defined as the frequency when the current gain is reduced to 1. input current = vG here is ac signal CG is approximately equal to the gate capacitance,  W L Cox output current = At the cutoff frequency (wT = 2pfT): Higher MOSFET operating frequency is achieved by decreasing the channel length L EE130/230A Fall 2013 Lecture 21, Slide 19