KRB proposal (Read Board of Kyiv group) Module 0 Segment 1 Segment 2 KRB + WOM 1 KRB + WOM 4 KRB + WOM 2 KRB + WOM 5 KRB + WOM 3 KRB + WOM 6 KRB + WOM 1 KRB + WOM 2 KRB + WOM 3 KRB + WOM 4 KRB + WOM 5 KRB + WOM 6 Gigabit Ethernet Gigabit Ethernet 6 6 External control and monitoring

KRB FPGA + ARM(Linux) ADC (DRS4) ADC (DRS4) KRB proposal PMT SiPM SiPM PMT channel PMT Analog filtering and processing SiPM SiPM FPGA + ARM(Linux) Branch of fast channel ADC (DRS4) SiPM Analog filtering and processing 8 Ch SiPM Ethernet SiPM Branch of PMT channel ADC (DRS4) Analog filtering and processing SiPM SiPM 9 Ch (8 SiPM + PMT) SiPM Power and monitoring

Kyiv group proposes the development of special Readout Board in the frame of development process for Prototype 1 with full functionality, after tests of this Readout Board (KRB) and investigations of KRB features decision will be made to take all features or only part of possibilities of KRB. For Module 0 the set of KRB boards (12 boards) will be have produced for complex tests of the readout devices from photodetectors taking into account the interconnections of KRB boards in inner area of Module 0 and with outer system of monitoring, control and data acquisition for offline analysis (or analysis of data with low intensity).

Each KRB board is intended for data acquisition and first analysis of signals from one WOM tube (8 input channels from SiPM photodetectors and one channel from PMT) Analog input channel for PMT will have: High Voltage supply (optionally, if it is needed) with voltage range 500 - 1300 V and adjustment of voltage with step < 1 V; circuit of signal forming; amplifier Each (from 8) analog input channel from SiPM will be split on the two branches: branch of Fast Signal and branch of Amplitude Signal. The branch of Fast Signal supports signal length not more than 10 ns from one photon due to circuit of signal shaping or special signal from SiPM (with optimal characteristics to obtain the best time resolution), bandwidth of this branch 900 MHz and amplifier coefficient <10 (to support input signals with rise time <1 ns); The branch of Amplitude Signal has optimal characteristics to obtain the best amplitude resolution, bandwidth 500 MHz and amplifier coefficient <10)

Analog signals from each branch are sent to the scheme of digitizing (on the base of the chip DRS4, for each branch - own scheme); Range of time sampling for DRS4 – from 5 GSPS to 0.7 GSP. Time of ADC conversion – 33 µs (for 1024 time points) or less (if number of time points less than 1024, 33 ns on time point), for example for 25 time points the dead time will be about 1 us ---> maximum rate is 100.000 per sec roughly, with detection efficiency 90%). If (it is optionally) one use DRS4 digitizing scheme for Amplitude Signal in "zero dead time" mode, detection efficiency can approach to 99%

Optionally - for branch of Fast Signal we plan to use Time-Digital- Conversion technique (or TDC FPGA) for obtaining of signal amplitude Triggering of conversion start (input signals from 8 SiPMs using fast comparators) We plan to support of all control and monitor signals, using set of FPGA and ARM processor with RAM 512 MB (for Master Boards value of RAM may be increased), supporting OS for ARM processor – full scale Linux OS Interconnections and data exchange between the KRB boards in the inner area of Module 0 and with outer system will be carried out using Gigabit Ethernet through standard switch

Time milestones Power supply for 8 SiPMs Voltage in the range 15 - 80 V Adjustment of voltage with step < 1 mV Monitoring of voltage and current of each SiPM Time milestones For development of first and second prototypes of block we need 1 year After successful completion of p.1 (with tests) we will be ready to produce 12 blocks – during 4 months.