From SNATS to SCATS C. Beigbeder1, D. Breton1,F.Dulucq1, L. Leterrier2, J. Maalmi1, V. Tocut1, Ph. Vallerand3 1 : LAL Orsay, France (IN2P3 – CNRS) 2 : LPC Caen, France (IN2P3 – CNRS) 3 : GANIL Caen, France (IN2P3 – CNRS) Journees VLSI Juin 2010

An electronics chain for SuperB FDIRC SuperB FDIRC (Frascati) BABAR DIRC (SLAC) Journees VLSI Juin 2010

Electronics requirements for PID barrel ~ 18000 Channels. Time resolution: ~100 ps for the electronics. Charge measurement option for all the channels. => both for physics and for timing correction (time walk) Count rate per channel : in worst case up to ~ 1 MHz. 150 KHz trigger rate. 6 us trigger latency. Min double pulse resolution : 50ns. Journees VLSI Juin 2010

SNATS: Evolution & Perspectives Not adapted for SuperB: - Dynamic Range: 53 bits -> Time coverage: 20 days - Max hit rate : 150 kHz per chip Need to reduce dead time due to : - readout protocol between ASIC and PGA -> 50 ns per 16 bit word - Interface between frontend and Readout to be redesigned INL, DNL, resolution … : same requirements Journees VLSI Juin 2010

SNATS: Evolution & Perspectives 2 possible options (among many others …) Keeping almost the same design and just adding a FIFO at the output. it increases the input channel rate in burst mode but keeps the average readout rate like the previous version. The FIFO size is costly. Keeping the Gray counter inside the ASIC with an output bus width set by user in order to reduce the amount of data to be transferred. The Gray counter is duplicated inside the associated PGA. The serial output is synchronous with the clock to ensure the matching between the 2 counters. 16 differential output channels @ 80 MHz (160MHz?). Max performance : MHz/channel in burst mode but limited by the size of the FIFO. Max performance 5 DLL bits + 4 Gray bits + start bit = 10b @ 80 MHz -> 8MHz input rate ! Linked to performance of the readout acquisition Journees VLSI Juin 2010

SCATS is somewhere in between … Instantaneous Dead time ~25ns Readout dead time Output Max speed~40 MHz Push the data Journees VLSI Juin 2010

New design of the Readout part Programmable number of bits for the coarse time counter Decreases the time transfer to the register Gray –> Binary encoder in case of truncation The 16 channels are consecutively output thanks to a global state machine (GSM) @ 80 MHz. - No handshake -> data pushed architecture with data ready flag - Sequential output -> min/max predictable latency The 16 bit event data word can contain between 1 and 4 words. Counter [10:0] 5-bit DLL Counter [26:11] Counter[42:27] Counter[47:43] Error Bits Journees VLSI Juin 2010

New design of the Readout part (2) Derandomizer FIFOs: store up to 16/32 events (4*16-bit data word). If the hit rate goes higher, in order not to overcome the output bandwidth, the required dead time and the event size have to get reduced. This is done by reducing the number of words per event stored in the FIFO. Global reset : synchronization over the whole system : absolute time – Multi chips … Channels & states machines Resets . Channel disable : to kill noisy channels Fifo Full flag: associated with the channel readout FIFO read/write pointers monitoring flag SEU mitigated. Based on the LHCb calorimeter front end electronics. Journees VLSI Juin 2010

Expected Performances Bin size (LSB) ~ 200 ps Clock frequency 160 MHz Single pulse mode Resolution ~ 70 ps RMS DNL ( / max) ~  0.1 LSB INL ( / max) ~  1 LSB Crosstalk <  0.2 bin Dead time : ~ 25 ns Number of data words per event 4 2 1 Readout frequency per channel (All channels fired) 1,25 MHz 2,5 MHz 5 MHz Max readout frequency per channel (only one channel fired) 20 MHz 40 MHz 40 MHz Techno : AMS 0.35u Milestones : Submission end 2010 Journees VLSI Juin 2010