HW5: Mentor Graphics I “ Design of a CMOS Inverter”

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Presentation transcript:

HW5: Mentor Graphics I “ Design of a CMOS Inverter” Osamah Rawashdeh EE584 Fall 02

Overview Schematic Capture (Design ArchitectTM) Functional Simulation (Quicksim IITM) Layout (IC StationTM) Analog Simulation (Accusim IITM)

Schematic in Design ArchitectTM Transistor-level schematic capture Symbol creation Viewpoint creation

Logic Simulation in Quicksim IITM Only functional correctness is examined

Inverter Layout in IC StationTM Channel length = 2 λ Channel width n-MOS = 5 λ p-MOS = 10 λ Metal rail width = 5 λ Contacts = 2 λ x 2 λ Cell pitch = 50 λ Cell origin set Inverter layout conforms to DRC and LVS rules

Analog Simulation in Accusim IITM Simulation is based on parameters extracted from physical layout

Measurements in Accusim IITM Design and verification of a CMOS inverter concluded.