COCO - Session #19 Today: Get to know the Logic State Analyzer Build the counter that you designed in Session #18, and test it - Hardware building activity - Display your results on the analyzer

Logic State Analyzers a tool for observing logic states of multiple signals at once, in time A logic probe can show only one bit at a time. Extremely useful tool for testing and debugging sequential circuits!!

Summary Hardware version of the “timing window” on LogicWorks Capture, store, and display up to 16 time-varying signals simultaneously Variety of ways to start/stop capture Make time and frequency measurements e.g., circuit delay measurements, setup and hold times Detect glitches More info on web http://www.tmo.hp.com/tmo/datasheets/English/HP54620A.html Manuals available in lab cabinet

HP54620A Specifications up to 500 million samples/sec sweep speeds of 5ns/div to 1 s/div about 2K bytes of data storage minimum detectable glitch 3.5ns Timebase accurate to 0.01% of reading can be interfaced with PCs and other instruments can print data

DISPLAY 16-BIT SIGNAL INPUT These cables are stored behind the screens. MICRO GRABBERS POWER SWITCH PROBE LEADS

CHANNEL CONTROLS Select Channel Assign Labels Set Position HORIZONTAL CONTROLS Adjust timing

GENERAL CONTROLS Measuring time Saving Display and print “SOFT KEYS” Their functions change with context

TRIGGER KEYS Specify kind of triggering (edge/pattern/…) TRIGGER INPUT/OUTPUT External trigger signal Signals to trigger external systems

The Screen 0 Out 1 A 2 B Ext _ Sampling @ 16ns GL 0.00s 2.00 µs/ RUN Sampling @ 16ns GL 0.00s 2.00 µs/ RUN 0 Out 1 A 2 B Activity = 15 _ _ _ _ _ _ _ _ _ _ _ _ _ 0 Ext _ Source Edge 0 Out E Trg In

Delay Sampling Interval Glitch Mode Sampling @ 16ns GL 0.00s 2.00 µs/ RUN 0 Out 1 A 2 B Activity = 15 _ _ _ _ _ _ _ _ _ _ _ _ _ 0 Ext _ Source Edge 0 Out E Trg In

Time/div Trigger Condition Acquisition Indicator Sampling @ 16ns GL 0.00s 2.00 µs/ RUN Acquisition Indicator 0 Out 1 A One “Division” 2 B Activity = 15 _ _ _ _ _ _ _ _ _ _ _ _ _ 0 Ext _ Source Edge 0 Out E Trg In

0 Out Move these using the cursor control knobs 1 A Memory Bar Soft Sampling @ 16ns GL 0.00s 2.00 µs/ RUN 0 Out Move these using the cursor control knobs 1 A Memory Bar Soft Keys Measurements 2 B Activity = 15 _ _ _ _ _ _ _ _ _ _ _ _ _ 0 Ext _ Source Edge 0 Out E Trg In

Questions? Manuals are in the cabinet! 0 Out 1 A 2 B Ext _ Sampling @ 16ns GL 0.00s 2.00 µs/ RUN 0 Out 1 A Manuals are in the cabinet! 2 B Activity = 15 _ _ _ _ _ _ _ _ _ _ _ _ _ 0 Ext _ Source Edge 0 Out E Trg In

Please do the Activity Now Remember that the logic analyzer is a delicate instrument. Handle it gently. Don’t force anything!! Build and test the fancy counter that you developed in the previous class with JK Flip Flops (74LS109) using real TTL hardware Display the output of your circuit on the HP logic state analyzer