Dave Lim and John Lockwood Washington University, Simulation of the Hello World Application for the Field-programmable Port Extender (FPX) Dave Lim and John Lockwood Washington University, Applied Research Lab http://www.arl.wustl.edu/arl/projects/fpx/ Fall 2001 Gigabit Kits Workshop Supported by NSF-ANI-0096052 and Xilinx Corp

Problem Statement General Statement Details “Implement a plug-in module that monitors a traffic flow. For cells with payloads that begin with “Hello”, have the module replace the following bytes with “World”. Details Scan Flows on VCI=5 Match the content of the cell for the “HELLO” ASCII: “HELLO” Hex: 48 – 45 – 4C – 4C – 4F Binary: 0100,1000 - 0100,0101- 0100,1100 - 0100,1100 - 0100,1111 Replace following contents with “WORLD.” ASCII “WORLD.” Hex: 57 – 4F – 52 – 4C – 44 – 2E Binary: 0101,0111 – 0100,1111 – 0101,0010 – 0100,1100 – 0100,0100 – 0010,1110

“Hello, World” Module Function

Case 1: Mismatched VCI Only process Cells on the selected VCI All other flows should pass unchanged

Case 2: Mismatched Source String Cell payload must contain “HELLO” in payload. “MELLO”  “HELLO”

Case 3: Mismatched Source String [word 2] Payload must match over entire string. Data arrives as streaming words

Hello World Block Diagram tcaff_sw_rad tcaff_sw_nid soc_sw_nid soc_sw_rad d_sw_nid O_WO d_sw_rad RLD NUL data_sel cnt_en data_in cntr_output hellofsm counter_4_bit soc_in ld_cntr cntr_output init_cntr_val rst_cntr data_sel clk reset clk reset

Finite State Machine Bubble Diagram SOC=“1” VCI=5 Data_in=“HELL” Init Pad Hell_check O_check SOC=“1” VCI/=5 SOC=“1” cnt=“1101” Data_in/=“HELL” Data_in/=“O” SOC=“0” cnt=“1101” Dout Wo_rld Data_in=“O”

Module Implementation D_MOD_IN[31:0] D_MOD_OUT[31:0] Data Interface SOC_MOD_IN SOC_MOD_OUT TCA_MOD_OUT TCA_MOD_IN Module Logic X SRAM_GR SRAM_REQ SRAM_D_IN[35:0] SRAM Interface SRAM_D_OUT[35:0] SRAM_ADDR[17:0] SRAM_RW X SDRAM_GR SDRAM_REQ SDRAM_DATA[63:0] SDRAM_DATA[63:0] SDRAM Interface SRAM_ADDR[17:0] SRAM_RW CLK Module Interface RESET_L ENABLE_L READY_L

Hello, World Entity RAD RAD_Loopback_Core

TestBench configuration INPUT_CELLS.DAT rad_loopback Fake_NID soc Data tcaff rad_loopback_core NID_Out HelloWorld_module NID_In loopback_module CELLSOUT.DAT soc Data tcaff

Download Files Visit Download HelloWorld Testbench http://www.arl.wustl.edu/arl/projects/fpx/workshop_0801/ Download HelloWorld Testbench Right-click on Hello.tar Save Target in: h:\ Access Files in Cygwin Bash Shell Start > Engineering > FPGA Tools > Cygwin Bash Shell cd /cygdrive/h/ gunzip Hello.tar.gz tar xvf Hello.tar cd HelloFiles ls shows three folders: ./sim, ./syn, ./vhdl

Manifest of Files in Hello.tar http://www.arl.wustl.edu/arl/projects/fpx/workshop_0801/HelloFiles.tar Contains: Makefile: Build and complile programs INPUT_CELLS.DAT: Cells written into simulation (Hex) modelsim.ini: Sets path for libraries needed for compiling and simulating testbench.vhd: Testbench for RAD fake_NID_in.vhd: Utilities to save cells to file fake_NID_out.vhd: Utility to read cells from file clock.vhd: Utility to read cells from file rad_loopback.vhd: Top-level design rad_loopback_core.vhd: Core that instantiates helloworld_module loopback_module.vhd: Module that passes data through unchanged blink.vhd: Blinks LED when RAD module is downloaded onto FPX helloworld_module.vhd: Top-level helloworld design hellofsm.vhd: Hellworld finite state machine counter_4_bit.vhd: Counter that counts number of words received mux4vhd: Multiplexor for selecting outputs data_flop.vhd: Output flop for data soc_flop.vhd: Output flop for SOC signal tca_flop.vhd: Output flop for TCA signal rad_loopback.ucf: Pin mapping for RAD FPGA bitgen.ut: Options file for generating .bit file build: Script file for creating the backend

Source: Multiplexor (from mux4.vhd) entity mux4 is port (a, b, c, d : in std_logic_vector(31 downto 0); sel : in std_logic_vector(1 downto 0); output : out std_logic_vector(31 downto 0)); end mux4; architecture behavioral of mux4 is begin mux_process: process (sel,a,b,c,d) case sel is when "00" => output <= a; when "01" => output <= b; when "10" => output <= c; when "11" => output <= d; when others => output <= a; end case; end process mux_process; end behavioral;

Source: State transitions (from hellofsm.vhd) state_trans:process(state,soc_in,cntr,data_in) begin case state is when init => if (soc_in='1') then if (data_in(19 downto 4)=x"0005") then nxt_state <= pad; else nxt_state <= dout; end if; nxt_state <= init; when pad => nxt_state <= hell_check; when hell_check => if (data_in=x"48454c4c") then nxt_state <= o_check; when o_check => if (data_in(31 downto 24)=x"4f") then …

Source: Next State Assignments (from hellofsm.vhd) clkd:process(clk) begin if (clk'event and clk='1') then if (reset='0')then state <= init; else state <= nxt_state; end if; end process clkd;

Contents of TESTCELL.DAT (1st Cell) new_cell Indicates new cell 00000050 VCI=5 E2000000 48454C4C 1st Payload word = “HELL” 4F000000 2nd Payload word = “O” 00000000 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038 00000039

Contents of TESTCELL.DAT (2nd Cell) new_cell Indicates new cell 00000040 VCI = 4 92000000 48454C4C 1st Payload word = “HELL” 4F000000 2nd Payload word = “O” 00000000 00000031 00000032 00000033 00000034 00000035 00000036 00000037 00000038 00000039

Simulation (Makefile) go into sim directory cd sim type “make newsim” Create a work directory to compile all the VHD designs into type “make compile” Compile all VHD designs type “make sim” Simulate top-level design using modelsim

Viewing Signals in Modelsim type “view structure” opens a window that allows you to view the overall design structure in a hierarchical fashion type “view signals” opens a window that allows you to pick out signal waveform that you want to look at during simulation type “view wave” opens a window for waveforms type “add wave -r /*” add all the waveforms in design from signals window, [View menu] > signals > selected signals add individual signals Run simulation type “run 1000”

Synthesis (Start Synplicity) click Start > Engineering > FPGA Tools > Synplify Pro Open project in Synplicity click Open Project… > New Project...

Synthesis (Save project and add files) File > Save save project under h:\hellofiles\syn\ Add VHDL files click Add File.. go to HelloFiles\vhdl\ highlight all .vhd files click <-Add click OK Make sure VHDL files are in correct order make sure that rad_loopback.vhd is last module; helloworld_module.vhd and rad_loopback_core.vhd are just above it

Synthesis (Set Implementation Options and Run) click Impl Options… Under Device Technology: Xilinx Virtex-E Part: XCV1000E Speed: -7 Package: FG680 Under Options/Constraints Frequency(Mhz): 100 Implementation Results Implementation Name: rad-xcve1000 Results Directory: h:\hellofiles\syn\rad_xcve1000 (if this gives you a warning, click ‘yes’) click Run save project

Synthesis (running the backend script) Try running backend script Go to /cygrdrive/h/HelloFiles/syn/rad-xcve1000 type “./build” Set path for Xilinx backend tools go to fpx workshop webpage under Synthesis for the 1pm session click on “cyg vars” copy and paste the commands into cygwin Run backend script again

Synthesis (backend script) part=xcv1000e-7-fg680 design=rad_loopback #ngdbuild - builds all the components into a ngd file ngdbuild -p ${part} ${design} -uc ${design}.ucf #ngd2vhdl - builds a post-synthesis vhdl file for simulation ngd2vhdl -w ${design}.ngd ${design}_sim.vhd #map - the logic components into xilinx specific logic gates map -p ${part} -o top.ncd ${design}.ngd ${design}.pcf #par - place and route the logic gates in the chip par -w -ol 2 top.ncd ${design}.ncd ${design}.pcf #bitgen - generates the bitstream bitgen ${design}.ncd -b -l -w -f bitgen.ut

Exercise Change VHDL code so that it says “HELLO GIGA BIT KITS WORK SHOP.” instead of “HELLO WORLD”. Changes need to be done to hellofsm.vhd, mux.vhd and helloworld_module.vhd

New Bubble Diagram Init Pad Hell_check O_check Giga1 Wo_rld Dout Shop1 SOC=“1” VCI=5 Data_in=“HELL” Init Pad Hell_check O_check SOC=“1” cnt=“1101” Data_in/=“HELL” Data_in=“O” Data_in/=“O” SOC=“1” VCI/=5 Giga1 Wo_rld Dout SOC=“0” cnt=“1101” Shop1 Work Giga2 Shop2 Kits Bit

Sample Cell

Hex / ASCII Table [See your Handout!] "Hex.txt" 34 lines, 1776 characters Hx Symbol (Function) Hx Char Hx Char Hx Char -- -------------------- -- ----- -- ---- -- ---- 00 NUL (null) 20 SPACE 40 @ 60 ` 01 SOH (start of head) 21 ! 41 A 61 a 02 STX (start of text) 22 " 42 B 62 b 03 ETX (end of text) 23 # 43 C 63 c 04 EOT (end of trans) 24 $ 44 D 64 d 05 ENQ (enquiry) 25 % 45 E 65 e 06 ACK (acknowledge) 26 & 46 F 66 f 07 BEL (bell) 27 ' 47 G 67 g 08 BS (backspace) 28 ( 48 H 68 h 09 TAB (horizontal tab) 29 ) 49 I 69 i 0A LF (line feed) 2A * 4A J 6A j 0B VT (vertical tab) 2B + 4B K 6B k 0C FF (form feed) 2C , 4C L 6C l 0D CR (carriage ret) 2D - 4D M 6D m 0E SO (shift out) 2E . 4E N 6E n 0F SI (shift in) 2F / 4F O 6F o 10 DLE (escape) 30 0 50 P 70 p 11 DC1 (devcontrol 1) 31 1 51 Q 71 q 12 DC2 (devcontrol 2) 32 2 52 R 72 r 13 DC3 (devcontrol 3) 33 3 53 S 73 s 14 DC4 (devcontrol 4) 34 4 54 T 74 t 15 NAK (nak) 35 5 55 U 75 u 16 SYN (synch idle) 36 6 56 V 76 v 17 ETB (end of block) 37 7 57 W 77 w 18 CAN (cancel) 38 8 58 X 78 x 19 EM (end of medium) 39 9 59 Y 79 y 1A SUB (substitute) 3A : 5A Z 7A z 1B ESC (escape) 3B ; 5B [ 7B { 1C FS (file separator) 3C < 5C \ 7C | 1D GS (group sep) 3D = 5D ] 7D } 1E RS (record sep) 3E > 5E ^ 7E ~ 1F US (unit sep) 3F ? 5F _ 7F DEL

Conclusions "Hello World” Illustrates: Example of simple hardware module implemented on the the RAD. Simple test program to check if tools are running correctly.

“Hello, World” References FPX Homepage http://www.arl.wustl.edu/arl/projects/fpx/ Hello World Handout John Lockwood, David Lim, "Hello World: A simple application for the Field Programmable Port Extender (FPX), Washington University, Department of Computer Science, Technical Report WUCS-00-12, July 11, 2000. http://www.arl.wustl.edu/arl/projects/fpx/references/hello_world_techreport.pdf Hello World Testbench http://www.arl.wustl.edu/arl/projects/fpx/workshop_0801/HelloTestbench.tar FPX Tool Environment http://www.arl.wustl.edu/arl/projects/fpx/workshop_0801/tools.html