Design Lab with SystemC 4541.633A SoC Design Automation School of EECS Seoul National University

Outline How to Download SystemC How to Install SystemC Download procedure OSCI homepage How to Install SystemC System Requirements Cygwin installation SystemC Installation notes Directory tree Running an example Useful SystemC Tools Simulation tools Debugging tools Examples Simple Counter DCT

How to Download SystemC Download procedure SystemC download website Visit OSCI home page: http://www.systemc.org About SystemC  Download (OSCI standards) Download what you want We assume Cygwin (Windows) for the OS throughout this lecture. Core SystemC language and examples ‘systemc-2.2.0.tgz’ You may need a registration for download.

How to Download SystemC OSCI homepage

How to Install SystemC System requirements For SystemC release 2.2.0 UNIX platform Sun Solaris Linux HP_UX Windows platform Windows NT with Visual C++ 6.0 Cygwin

SystemC Installation with Windows Cygwin Cygwin installation Cygwin is a UNIX environment, developed by RedHat, for windows. Installation guide Cygwin home page  http://www.cygwin.com Click 'Install or update now!' Run ‘setup.exe’ to get Cygwin packages Select “install from internet” Select install directory and local package directory Select “direct connection” Select your preferred ftp site Change ‘ALL@default’ to ‘ALL@install’ ‘C:\cygwin’ will be the installation directory

SystemC installation notes How to Install SystemC SystemC installation notes Uncompress the ‘systemc-2.2.0.tgz’ file on your working dir. - We assume current working directory is ‘/home/userid/works’ tar zxvf systemc-2.2.0.tgz Change to the top level directory (systemc-2.2.0) cd systemc-2.2.0 Create a installation directory and change to that directory, e.g., mkdir build cd build Configure the package for your system ../configure –prefix=/home/userid/works/systemc-2.2.0/build It will automatically generate the Makefile Compile the package > make (or gmake) Install the package > make install (or gmake install)

Directory tree systemc-2.2.0/ config/ docs/ examples/ msvc60/ src/ How to Install SystemC Directory tree systemc-2.2.0/ config/ docs/ examples/ msvc60/ src/ build/ include/ lib-cygwin/ Install directory that contains ‘systemc.h’ header file and ‘libsystemc.a’ system-dependent library file

How to Install SystemC Running an example Move to the directory for pipe example (e.g. systemc-2.2.0/examples/pipe/ ) > cd ./examples/sysc/pipe/ Read the brief description of the example in the ‘README’ file Build the example using make > make check

How to Install SystemC Run the executable ./pipe

GTKWave: electronic waveform viewer Useful SystemC Tools Useful SystemC Tools GTKWave: electronic waveform viewer Viewer for waveforms in [VCD/EVCD/LXT/Synopsys] output format Built using the GTK+ toolkit GTKWave home page http://www.cs.manchester.ac.uk/apt/projects/tools/gtkwave GTKWave installation with Cygwin Get ‘gtkwave-1.3.19-setup.exe’ from ftp://ftp.cs.man.ac.uk/pub/amulet/gtkwave/1.3/ Run ‘gtkwave-1.3.19-setup.exe’, which is self-extracting installation program Make a symbolic link as follows ln –s /cygdrive/c/Program\ Files/GTKWave\ 1.3.19/winwave.exe /usr/local/bin/gtkwave

Useful SystemC Tools ModelSim 6.2 Unified kernel for Verilog, VHDL, and SystemC for a true mixed-language environment Requires optional product add-on to ModelSim 6.2 SE/LE An additional license is required Download website http://www.model.com/downloads/default.asp

Debugging tools GDB INSIGHT DDD GNU source-level debugger Useful SystemC Tools Debugging tools GDB GNU source-level debugger http://www.gnu.org/software/gdb/ INSIGHT Graphical user interface to GDB http://sources.redhat.com/insight/ DDD Data display debugger http://www.gnu.org/software/ddd/

Examples Simple Counter Environment Function SystemC-2.2.0 Cygwin with gcc compiler GTKWave waveform viewer Function Count from ‘0’ to ‘255’ Reset signal set cntvalue[7:0] signal to ‘0x00’ If count it up to ‘255’, overflow signal is set to ‘1’.

Simple counter block diagram Examples Simple counter block diagram testbench count reset overflow cntvalue[7:0] clk clk clock

Counter module: counter.h Examples Counter module: counter.h in/out ports process function data member process registration sensitivity list initialization

Counter module: counter.cpp Examples Counter module: counter.cpp reset behavior Increase the ‘local_cntvalue’ on clock rising edge overflow detect ‘local_cntvalue’ to cntvalue port

Examples Testbench module

Top level 10 ns module instantiation & pin connection Examples Top level 10 ns module instantiation & pin connection trace file (wave.vcd) generation SystemC simulation start for ‘simul_time’

Examples Makefile

Examples Compilation make

Simulation reset  restart the count Examples Simulation reset  restart the count overflow  set overflow signal & restart the count

Waveform ‘wave.vcd’ file is generated after executing the ‘run.x’. Examples Waveform ‘wave.vcd’ file is generated after executing the ‘run.x’.

Append the signal names to waveform list Examples Append the signal names to waveform list

Examples Simulated waveform

Examples Reset test

Examples Overflow test

Algorithm level DCT simulation Examples Algorithm level DCT simulation Functional block diagram Data Gen function (for input data setup) FDCT function ‘sample1’ ‘result’ fdct(in, out) Implemented in C code

FDCT source code in C ‘fdct_ref.c’ from MPEG Software Simulation Group Examples FDCT source code in C ‘fdct_ref.c’ from MPEG Software Simulation Group Forward DCT  8x8 matrix of 16-bit data value

Input/output of ‘fdct’ function Input: ‘sample1’ Output: ‘result’ Examples Input/output of ‘fdct’ function Input: ‘sample1’ Output: ‘result’

Timed level DCT simulation Examples Timed level DCT simulation Top level block diagram f_in[64] f_out[64] DataGen Module FDCT Module Sink Module request ready valid ack clock

Assignment These files are given from presentation. Examples Assignment These files are given from presentation. header files data_gen_sc.h sink_sc.h c++ files data_gen_sc.cpp sink_sc.cpp main.cpp Make file Makefile Sample file sample1 You can make your own fdct module. header file fdct_sc.h c++ file fdct_sc.cpp

DataGen Module data_gen_sc.h 64 parallel output port Examples DataGen Module data_gen_sc.h 64 parallel output port ports for handshake text file pointer for read data set file pointer to ‘sample1’ text file read and send data to fdct module & synchronize

Examples data_gen_sc.cpp Data_gen_module::set_input(char*)

Data_gen_module::do_gen() Examples Data_gen_module::do_gen()

fdct module & synchronize Examples Sink module sink_sc.h 64 parallel in port ports for handshake read data from fdct module & synchronize

Examples sink_sc.cpp

Examples Top module main.cpp

This file is same with ‘exmple1’ Examples Makefile & sample1 files This file is same with ‘exmple1’

void init_fdct(void); Examples FDCT module (HW) Now, you can make your own FDCT module. FDCT Module f_in[64] f_out[64] member variables double c[8][8]; double tmp[64]; in[64] out[64] f_req f_rdy req rdy member function void init_fdct(void); f_vld f_ack ack vld process function void do_fdct(void); clk

::init_fdct() ::do_fdct() Examples ::init_fdct() You can use the same behavior code that is used at algorithm level simulation ::do_fdct() 1. call init_fdct();  To initialize coefficient (c[8][8]) 2. send request to DataGen module; 3. while( vld==0 ) { wait(); } 4. turn off the request signal 5. while( vld==1 ) { wait(); } 6. delay computation cycles (8 cycles) 7. write code for DCT  read input data into temp[64] and run DCT 8. set ready so that Sink module can receive the data 7. while( ack==0 ) { wait(); } 9. turn off the ready signal 10. while( ack==1 ) { wait(); }

Compile & Simulation make ./run.x sample1 Examples Compile & Simulation make ./run.x sample1 The result is same as c code does.

Run ‘gtkwave’ waveform viewer Examples Run ‘gtkwave’ waveform viewer

Examples The waveform 8 cycle execution

Discussion Latency of DCT function Timed vs. Untimed Simulation speed Examples Discussion Latency of DCT function The waveform has been obtained by setting the latency of DCT function to 8 cycles. Cycle accurate model can be obtained thru ‘wait()’ annotation. Timed vs. Untimed SystemC supports both timed and untimed models. Simulation speed Faster than other HDL simulators