SVT front-end electronics Mauro Citterio INFN Milano On behalf of SVT group

SVT System SuperB SVT  similar to BaBar SVT + Layer 0 Layer 0 technology (baseline for TDR)  Hybrid pixels (50x50 mm2 pitch) Still under evaluation for layer 0: MAPS and Pixel V_I for improved performances Layer 1- Layer 5  double sided silicon detectors 300 um thick Each SVT layer is built of indepedent “modules” (52+8) One module is divided in two independent “half modules” Each half modules contains several “components”: Sensors Front-end chips Interfaces with power/signal inputs and data output link Layer 0: BUS and “HDI hybrid” Other layers: hybrid/readout ICs Module support/cooling Layer 0

SVT baseline configuration (1) Layer Radius 0 1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm Layer 0: Hybrid Pixels Radius: ~ 1.5 cm Module length: ~ 10 cm Pixel Pitch: 50x50 mm2 Hit Rate: 110 MHz/chip (safety > 5) Module Rates: 660 MHz Link Bandwidth: 20 Gbps Full Rate (FE data push) 3 Gbps Triggered Rate Power consumption: ~ 2 W/cm2 in the active area ~ 50 (mW/Gbps)/cm2 in HDI Total material budget: ~ 1% X0 Si sensor + FE chips 0.40 % X0 Al Bus + SMD comp. 0.34 % X0 Support & cooling ~ 0.3 % X0 BUS HDI: ~ 13 x 70 mm2 Power/Signal Data Half Module: 6 Sensors Carbon Fiber Support

SVT baseline configuration (2) Layer Radius 0 1.5 cm 1 3.3 cm 2 4.0 cm 3 5.9 cm 4 9.1 to 12.7 cm 5 11.4 to 14.6 cm External Layers: Double sided silicon detectors 300 um thick Radius: BaBar radii for the 5 layers Module length: similar to BaBar radii for the 5 layers Structure: L1-L2-L3 barrel shape L4-L5 arch shape Extend coverage down to 300 mrad FW and BW In BaBar it was 300 mrad FW and 520 mrad BW Link Bandwidth: < 1 Gbps Full Rate (FE data push) < 100 Mbps Triggered Rate Power consumption: ~ 1 W/cm2 in HDI Work ongoing using IC (FSSR2) that will require only minor modifications for SuperB HDI design partly “inherited” by the layer 0 HDI design HDI Si Wafers Data Power/Signal Front-end chips

Layer 0 Front-end electronics  Details in SVT presentations R&D work reorganized to prepare a baseline for TDR Layer0 based on hybrid pixels Better chance to meet the Layer0 requirements for the TDR timescale First front-end chip & pixel sensor in production in Sept. ’09 Continue R&D on thin pixels technology (SLIM5VIPIX Collaboration-INFN) CMOS DNW MAPS + Vertical Integration technology very promising for Layer 0 but not yet mature for TDR timescale. First DNW MAPS chip realized with two thin CMOS layers interconnected First results by end of 2009 If positive could be seriously considered for Layer0 performance improvement In either case the “digital interface” of the front-end electronics will be the same Based on APSEL5D design Completely data driven architecture Space time coordinates Time granularity 0.2-5.0 us (1.0 us is the goal) Time stamping is EXTERNAL. Hit rate expected: 110 Mhit/s/chip (with a safety factor > 5)

300 m for bonding on each bus side Layer 0 Bus Design Basic requirements: Layer 0 BUS design derived by previous CERN experience with ALICE bus Aluminum-Kapton technology used SuperB specification are challenging High signal trace density  up to ~ 200 signal lines Data speed on each line  up to 160 MHz (parallel bus ~ 30 lines) Minimum thickness  goal for thickness < 300 mm Sensor/readout interconnection  by wire bonding Max current on a power plane  up to 5 Amp 400 µ Glue 5µ Polyimide 40µ Aluminium 50µ Aluminium 13µ 300 m for bonding on each bus side Digital ground Digital power supply Horizontal signal lines Vertical lines Analogue power Analogue ground 15µ A prototype design exists and is under production Line widht and spacing ~ 75 mm Dielectric thickness ~ 40 mm Impedance ~ 50 W Overall estimated thickness (not optimized!) ~ 400 mm

HDI Design (optical solution) Hybrid Dimension (~ 13 mm x 70 mm x 15 mm)  It maybe accomodates up to two optical links (total data rate ~ 10 Gbps) Receiver, Glue Logic and Memory under design First prototype of CMOS SRAM rad-tolerant memory received (~ 0.5 MB) and under test, result will reported at the next meeting ASICs to “organize” the data coming from the bus and to prepare the data for the serializer: specs not yet finalized, design not started yet FPGA Ctl board based on Xilinx Virtex will be used for prototyping (> 300 user defined I/O pins, RAM) instead Rad-hard serializer: an IC called “LOC1” developed in SOS by SMU Dallas (2.5 Gbps) a LOC2 at 5 Gbps available by the end of 2009 Laser drivers: commercial (TX L2701and Micrel SY88992L) devices and GBT-LD under investigation Duplex LC package for housing two VCSEL and fibers  SPACE is a concern To DAQ EDRO EPMC EPMC Optical Fiber 60/80 MHz

HDI Design (copper link) Elements on the hybrid: Share BUS data receiver, glue logic, memory and serializer of the “Optical link” solution Differs in term of output drivers we are evaluating three different commercial (very low-jetter) drivers from MICREL SY58600U (CML), SY58602U (400 mV LVPECL driver) operating up to 10.7 Gbps SY58601U (800 mV LVPECL driver) operating up to 5 Gbps typical copper link length ~ 3-5 m increasing the length means “high power devices”  not really feasible Goal  propose a 2 or 4 copper lines solution on a maximum copper lenght Buffering Modulations Drivers Hp. All data out Cu bus < 20 Gbit/s Optical link 2.5 Gbit/s Edro like ROM Off detector low rad area Counting room On detector High rad area

HDI Design (mixed technology link !) Dictated by space constraints: Very likely not enough space for multiple optical links on the HDI near the detector In this mixed-link solution, the HDI will drive a short copper link Serializer must be capable of driving ~ 30 – 50 cm LOC barely capable of doing so The “transition card” will be active a “rad-tolerant” receiver must be found some work on going at CERN for IBL  ongoing contacts and discussion radiation level need to be understood  to investigate commercial solution, if any the combination <controls, laser driver, VCSELs, fiber optic packages> still the same volume on the transition card to be agreed upon Optical link 2 x 5 Gbit/s Transition Card: Receiver +laser+VCSEL Buffering Modulations Drivers Cu bus EDRO Near detector “soft” rad area Counting room On detector High rad area

EDRO Readout board Front End Card used in Slim5 beam test (SVT par. II): Main concept: flexibility at all levels Mezzanines to decouple input/processing/output Large FPGA Several triggering schema Slink To DAQ SuperB: 60 Mhz bus clocks 20 Gbit input rate 2.5 Gbit output rate New board version under design Performances: 40 Mhz bus clocks 8 Gbit input rate 1 Gbit output rate 2.5 ME/s evaluated @L1 40 kHz DAQ rate @slim5 Data from FE chips 4 Gbit/s EPMC Stratix EPMC TTCRQ Not too far from SuperB needs

Test set-up … under construction Data generated via FPGA Receiver + Glue Logic emulated via a custom made controller board designed in collaboration with Sanitas EG Serializer Clock in Serializer IC designed only after TDR approval Output Drivers Status: Fan out boards: under design FPGA boards: firmware in progress Hybrid: PCB design + evaluation boards Serializer: OK, LOC chips from Dallas + CERN Laser Driver: ordered (Micrel) VCSEL + package + fiber: ready to order Copper cable: variable lenght Receiver and Laser Drivers VCSEL double LC package

SVT in trigger and DAQ schemas Current best FE chip candidates are data driven with an intrinsic time resolution of 0.2-1.0 us Interface between FE chips and SuperB trigger and DAQ will be provided by a board equipped with large FPGA, memory and optical links (i.e. flexible) Consequences SVT will fit both the fixed and variable L1 latency schema SVT readout time window of 1 us or larger will be handled in the HDI or off-detector electronics. Same for fixed or variable time window. SVT might have the possibility to provide information on events before L1 trigger (L1-L5 best, L0 maybe)

Conclusions Main SVT challenge: layer 0 rates, chips, data bus and data transmission Current best FE chip candidates are data driven Front End Card and/or HDIs with enough logic to fit different DAQ and L1 schemas Trigger rate >150 kHz, time window >=1 us Data volume: L1-L5: 6 kB with 1 us time window L0: 66 kBytes with 1 us time window and >5 safety factor SVT in trigger still conceivable, but extremely difficult