ETD/Online Summary D. Breton, U. Marconi, S. Luitz London collaboration meeting 09/2011

Synchronous, Pipelined, Fixed-Latency Main items of discussion this week Synchronous, Pipelined, Fixed-Latency

Test beam of Xilinx Virtex 5 Test beam on Xilinx Virtex-5 FPGAs performed last July Measured configuration error x-section due to SEUs Good agreement (factor of 2) between published an measured x-section Tested a benchmark link running at 2 Gbps  2100 bit-flips in config. memory needed to observe a link failure Very good agreement (<10%) of measurements with previous tests with emulated SEUs 0.5 kGy(Si)/year (a) => 4.1104 configuration bit-flips on our design/year .# of link failures/year = 20 (on average, even without implementing ANY recovery strategy, could be improved with recovery) Test beam data analysis to be completed (currents, analyze link failures and their causes) Next test beam on Xilinx Virtex 5 and Virtex 6 December 10th Still unclear if FPGAs are suitable to be used on-detector # of Config Errors Irradiation Stopped @ 71 Gy (Si) Time (s) Courtesy of Riccardo Cenci, Elba Meeting, May-Jun. 2011 Raffaele Giordano 1st SuperB Collaboration Meeting, London Sept. 2011

ROM (U.Marconi) FPGA – PC based implementation, suitable to run at the baseline expected trigger rate of 150 kHz presently under test. Data enters the PC through the PCIe interface at 14.5 Gb/s, of a theoretically available bandwidth of 16 Gb/s. The PC forward data to the HLT via a 10 GbE NIC board. Testing multi-core PC architecture for parallelism. The Linux driver writes event fragments at different RAM locations. Processes running on different cores which access the assigned dedicated RAM banks to fetch data. FPGA could be also used to implement the 10 GbE functionality, aiming to a compact, cheaper and reliable alternative. Input rate of small event fragments can be easily managed in this case.

CsI read-out by Lyso CSP electronic chain (Roma1) Trigger Main question here is linked to trigger time jitter, which has a direct influence on the dataflow, especially for sub-detectors with short window and lots of data (like SVT) Main problem for the trigger is the slow signal from CSI(Ti) which may degrade the time resolution of the trigger But APD readout and faster shaping looks promising ... Δt between two pin diodes (33ns rms) CsI read-out by standard electronic chain (Roma3) CsI read-out by Lyso CSP electronic chain (Roma1) PIN diode low gain High gain 500ns APD signal

A possible sketch of trigger system in SuperB DC and EMC trigger crates have a common interface (LVDS or optical) with pertaining sub-detectors. EMC(i) and DC(i) boards share a common hardware platform and only differ in firmware. Idea here is to take benefit of a custom VME64 backplane designed in Napoli for the ATLAS level 1 trigger high speed serialized interconnections between boards running at a few Gbit/s this interesting proposal has to be further studied, especially in terms of consistency with FCTS and ECS

Simulation of the derandomizer hardware Verilog model The goal of the study is to get a first flavour of the necessary derandomizer depth in order to maintain a limited dead-time. 3 fixed parameters at the system level: Mean Trigger Rate : R = 150 kHz Minimum Distance between triggers : 36ns, 54ns, … ? Required overall dead time : < 1% (?) => Includes contributions from trigger, derandomizer, detectors … 1 fixed parameter at the subdetector level: 4. Read out Window : W [Nb of 56MHz clock periods] Parameter to define properly at the subdetector level: 5. Nb of channels multiplexed at the output of the derandomizer to feed the link: N  the mean link occupancy is then defined by : Ratio = Average Payload/ Nominal Capacity = R.W.N.32 bits / 1.8Gbit/s Then the goal is to optimize the derandomizer depth for the required dead time Jihane Maalmi –Dominique Breton- Elba - May 2011

Jihane Maalmi –Dominique Breton- Elba - May 2011 A few simulation results Effect of derandomizer dead-time request Trigger Mean Rate : 150 kHz W varying between 10 and 30 (180 ns to 540 ns); Result : Derandomizer Depth [Nb of full events] Effect of the link occupancy Effect of the min distance between triggers Jihane Maalmi –Dominique Breton- Elba - May 2011

Conclusion about derandomizer study There is an opposite behavior of different sub-detectors : short time window, high multiplexing factor and reduced pile-up long time window, low multiplexing factor and high pile-up => here, pile-up helps because if saturates the dataflow in a clean way! In the case of variable event size, should we base the derandomizer depth on: - The average size ? (less depth but more potential pile-up) - The maximum size ? (minimum dead-time but maximum depth) Importance of a fast throttle for the optimization of the derandomizer depth. hard to implement a model of the derandomizer if the event size is random (to build the throttle )? The worst case will depend on the sub-detector implementation We will need a fast direct throttle between FEE and FCTS Return path of clock and control links could be used therefore The final goal of 1% of dead-time seems to be achievable with: a link occupancy of 80% a derandomizer depth of 16 and a min distance between triggers of 36ns !

About the TDR Our goal: define a baseline Deal with uncertainties / unknowns / Future upgrades Aim at implementation with existing components E.g. data link implementation – assuming only 1GBit/s links are available Specify reduced-performance baseline and its implementation and an upgrade path to nominal baseline – or – specify full-performance baseline (but larger # of links, larger cost) Keep system upgradeable (e.g. modular components) Proposed preference Single chapter seems most natural Depth of section hierarchy may be a problem Length may be an issue 4 chapters seems workable … but somewhat of a kludge Techboard suggestion: Intro/overview chapter in the front with intro to the detector 3 chapters ELEX, TRG, DAQ/Online

SVT FE Status Layer0 old beam pipe new beam pipe SVT Baseline for TDR - Striplets in Layer0 @ R~1.5 cm  Triggered FE chips - 5 layers of silicon strip modules  Triggered or data push FE chips Upgrade Layer0 to thin pixel for full luminosity run  more robust against background occupancy Data chain is slowly progressing by defining all elements Technical analysis on HDI, Serializer, Tail and Power cables First prototype of optical mezzanine card 4 optical links at 1 Gbit/s; FPGA Xilinx, 40/100 MHz clk (programmable)

G.Felici - London SuperB Workshop- Sep 2011 DCH Cluster counting option => higher bandwidth => more power on the end plate & larger and more expensive cables The use of COTS should be avoided on detector for power reason => dedicated ASICs G.Felici - London SuperB Workshop- Sep 2011

Christophe Beigbeder/ ETD PID meeting There are many developments and test benches under study, and new MCPMTs are being studied Analog board with 3 different designs for testing a low walk discriminator (<50ps ) and validating design of the front end electronics; also generating signal for charge measurement. The board is ready to be launched Mother board : embeds the 100ps TDC ( SCATS ) and the ADC, packs the data and sends it to the DAQ. It is designed to test the SCATS and equip different test bench. The form factor of the FE board and mother board is a module which will be installed on the CRT (SLAC). It will be launched soon. The SCATS TDC: latest post layout simulation has been presented. Submission is foreseen in November. Full custom FIFO : ~ 1 GHz access capacity >> 100 MHz needed Dead time is only 3% with 1 MHz rate on each channel. Many test benches will be installed in the different labs and a common policy has been defined for the software development To increase our vertical angular resolution we planned to use the charge sharing effect. The latest tests shows that the 8500 cannot do it by construction and if we want to keep the expected resolution we should go for the HM 9500 and by consequence double the number of channels. Christophe Beigbeder/ ETD PID meeting September 14th 2011

EMC EMC Forward BGO model study and first tests. Hypothesis under study : 1) 4400 Lyso crystals APD readout (in the WP) 2) 4400 BGO crystals APD readout (under study) 3) 820 CsI crystals instead of CsI(Tl) but babar geometry New photodetector (pentode) new electronics new.... 4) PWO...... EMC Barrel : 5760 CsI(Tl) Crystals from Babar Hypothesis under study : 1) Babar style preamp + fast time line for trigger adding an APD or SiPM 2)Try to get fast timing information only with original PIN. 3) New light detectors (costly need to change all PINs) BGO model study and first tests. L.Recchia simulation

BaBar IFR upgrade: LST readout status report SiPM samples by FBK have been characterized at different bias and temperature by W. Kucewicz from AGH-University of Science and Technology. The system used for characterization is based on a SiPM readout ASIC developed at AGH and it is suited for large scale characterization of SiPMs. a second beam test of the IFR prototype has been carried out at Fermilab. Some new features, like automated compensation of temperature related SiPM gain variation, have been succesfully applied. with the knowledge of radiation types and doses at different detector location provided by the background studies, it is now possible to plan effective irradiation tests a “compact” front end card based on the “EASIROC” ASIC and flash based FPGAs will be developed in time for the February 2012 test beam to read out one (or more) planes of the IFR prototype. The same “compact” board will be used in irradiation tests. I SuperB Collab. Meeting – QMUL Sep-13-2011 A.Cotta Ramusino for INFN-FE/Dip.Fisica UNIFE

Conclusion RAM-based FPGAs have been irradiated. First result do not permit fully concluding if they can be used on detector. Farther study and irradiation of new components are ongoing Derandomizer simulations were fruiful in terms of understanding the effect of different sources of dead-time and the different behaviors of subdetectors Key numbers seem to emerge (80% link occupancy, 36ns between triggers, 16-deep derandomizer), which has an influence on some system requirements Throttling mecanism has to be farther investigated The first direct observation of CSI(Ti) crystal signal are encouraging for the EMC barrel trigger, using an APD and accelerating the signal shape we should be able to reach our goal for the trigger jitter (36ns …) We have a better idea of how organizing the ETD chapters of the TDR the most probable option is to have a general introduction plus 3 dedicated chapters