Introduction Introduction to VHDL Entities Signals Data & Scalar Types Arrays & Records Logical & Numerical Operators

Hardware Description Languages (HDL)

Description Levels

What a designer really needs ?!

Why VHDL ?!

Before VHDL ..

Now with VHDL ..

Entities

Elements of an Entity

Elements of an Entity

Architectures

Behavioral Description

Behavioral Description

Behavioral Description

Behavioral Description

Packages .. !!

Packages in VHDL

Predefined Packages

Signals

Signals: bit & vectors

Vector’s width & order

Vector’s width & order

External vs. Internal Signals

Declaration of signals

Documentation

Documentation

Generic .. ?!

Generic Specification

Generic Applications

Generic Applications

Scalar type

Scalar type

Scalar type

Scalar type

Scalar type

Arrays

User-defined-arrays

Records

Logical Operators

Numerical Operators

Numerical Operators

Numerical Operators

Numerical Operators

Numerical Operators

Numerical Operators

Numerical Operators

Numerical Operators

Relational Operators

Constants

Use of Constants

Generic vs. Constant

Generic vs. Constant

Generic vs. Constant

Summary Introduction to VHDL Entities Signals Data & Scalar Types Arrays & Records Logical & Numerical Operators

Content Process Signals vs. Variables Conditional statement Loops Sequential & Parallel design Signals & Modules Test Bench Reporting

Structure of process

Structure of process

Structure of process

Structure of process

Structure of process

Process Execution

Sensitivity list and Signals in a Process

Sensitivity list and Variables in a Process

Sensitivity list and Variables in a Process

Sensitivity list and Variables in a Process

Signals vs. Variables

Signals vs. Variables

Signals vs. Variables

Controlling the sequence of statements

Conditional statements

Conditional statements

Conditional statements

Conditional statements with alternatives

Conditional statements with alternatives

Multiple Choices

Multiple Choices

Loop with a counter

Loop with a counter

Loop with a counter

Loop with a counter

The world is not sequential .. !!

How an architecture is executed

How an architecture is executed

How an architecture is executed

How an architecture is executed

Do you really need a process ?!

Do you really need a process ?!

Conditional Signal assignments

Conditional Signal assignments

Selected Signal assignment

Selected Signal assignment

Signals and modules

Signals and modules

Multi-level logic

Multi-level logic

Multi-level logic

Multi-level logic

Structural design

Elements of structural descriptions

Positional port mapping

Named port association

Complex port mapping

Component declaration

Component instantiation

Test Bench .. ?!

VHDL test bench

Elements of a VHDL test bench

Elements of a VHDL test bench

Using test benches

Using test benches

Using test benches

Using test benches

Unit Under Test

Unit Under Test

Unit Under Test

Unit Under Test

Stimuli of signals

Assert statement

Reporting with assertions

Summary Process Signals vs. Variables Conditional statement Loops Sequential & Parallel design Signals & Modules Test Bench Reporting

Good luck 

Finite State Machines (FSM) All programmable logic designs can be specified in Boolean form. However some designs are easier to conceptualize and implement using non-Boolean models. The State Machine model is one such model.

FSM A state machine represents a system as a set of states, the transitions between them, along with the associated inputs and outputs. So, a state machine is a particular conceptualization of a particular sequential circuit. State machines can be used for many other things beyond logic design and computer architecture.

FSM Any Circuit with Memory Is a Finite State Machine Even computers can be viewed as huge FSMs Design of FSMs Involves Defining states Defining transitions between states Optimization / minimization

Definition of Terms State Diagram Illustrates the form and function of a state machine. Usually drawn as a bubble-and-arrow diagram. State A uniquely identifiable set of values measured at various points in a digital system.

Definition of Terms Next State The state to which the state machine makes the next transition, determined by the inputs present when the device is clocked. Branch A change from present state to next state.

Definition of Terms Mealy Machine A state machine that determines its outputs from the present state and from the inputs. Moore Machine A state machine that determines its outputs from the present state only.

Present and Next State State 0 State 1 State 3 State 2 For any given state, there is a finite number of possible next states. On each clock cycle, the state machine branches to the next state. One of the possible next states becomes the new present state, depending on the inputs present on the clock cycle. State 2 State 3 State 1 State 0

Describe Outputs as Concurrent Statements Depending on State Only Moore Machine Describe Outputs as Concurrent Statements Depending on State Only transition condition 1 state 2 / output 2 state 1 / output 1 transition condition 2

transition condition 1 / transition condition 2 / Mealy Machine Describe Outputs as Concurrent Statements Depending on State and Inputs transition condition 1 / output 1 state 2 state 1 transition condition 2 / output 2

Moore and Mealy FSMs Can Be Functionally Equivalent Moore vs. Mealy FSM (1) Moore and Mealy FSMs Can Be Functionally Equivalent Mealy FSM Has Richer Description and Usually Requires Smaller Number of States Smaller circuit area

Mealy FSM Computes Outputs as soon as Inputs Change Moore vs. Mealy FSM (2) Mealy FSM Computes Outputs as soon as Inputs Change Mealy FSM responds one clock cycle sooner than equivalent Moore FSM Moore FSM Has No Combinational Path Between Inputs and Outputs Moore FSM is less likely to have a shorter critical path

Moore FSM Input: w Transition function Next State: y_next Present State: y_present Memory (register) Output function Output: z

Mealy FSM Input: w Transition function Next State Present State: y Memory (register) Transition function Output Input: w Present State: y Next State Output: z

Moore FSM that Recognizes Sequence 10 Moore FSM - Example Moore FSM that Recognizes Sequence 10 S0 / 0 S1 / 0 S2 / 1 1 reset S0: No elements of the sequence observed S1: “1” observed S1: “10” observed Meaning of states:

Mealy FSM that Recognizes Sequence 10 Mealy FSM - Example Mealy FSM that Recognizes Sequence 10 0 / 0 1 / 0 1 / 0 S0 S1 reset 0 / 1 S0: No elements of the sequence observed S1: “1” observed Meaning of states:

Moore & Mealy FSMs – Examples clock 0 1 0 0 0 input S0 S1 S2 S0 S0 Moore S0 S1 S0 S0 S0 Mealy

FSMs in VHDL Finite State Machines Can Be Easily Described With Processes Synthesis Tools Understand FSM Description If Certain Rules Are Followed State transitions should be described in a process sensitive to clock and asynchronous reset signals only Outputs described as concurrent statements outside the process

State Encoding Problem State Encoding Can Have a Big Influence on Optimality of the FSM Implementation No methods other than checking all possible encodings are known to produce optimal circuit Feasible for small circuits only Using Enumerated Types for States in VHDL Leaves Encoding Problem for Synthesis Tool

Types of State Encodings Binary (Sequential) – States Encoded as Consecutive Binary Numbers Small number of used flip-flops Potentially complex transition functions leading to slow implementations One-Hot – Only One Bit Is Active Number of used flip-flops as big as number of states Simple and fast transition functions Preferable coding technique in FPGAs

Types of State Encodings Binary Code One-Hot Code S0 000 10000000 S1 001 01000000 S2 010 00100000 S3 011 00010000 S4 100 00001000 S5 101 00000100 S6 110 00000010 S7 111 00000001

RTL Design Components Data Inputs Control Inputs Datapath Circuit Data Outputs

Datapath Circuit Provides All Necessary Resources and Interconnects Among Them to Perform Specified Task Examples of Resources Adders, Multipliers, Registers, Memories, etc.

Control Circuit Controls Data Movements in Operational Circuit by Switching Multiplexers and Enabling or Disabling Resources Follows Some ‘Program’ or Schedule Usually Implemented as FSM

Example Consider the following algorithm that gives the maximum of two numbers. 0: int x, y, z; 1: while (1) { 2: while (!start); 3: x = A; 4: y = B; 5: if (x >= y) 6: z = x; else 7: z = y; }

Example – Cont. Now, consider the following VHDL code that gives the maximum of two numbers. ----------------------------------------------------------------------------------------- entity MAX is generic(size: integer:=4); port( clk, reset, start: in std_logic; x_i, y_i :in std_logic_vector(size-1 downto 0); z_o: out std_logic_vector(size-1 downto 0)); end MAX; architecture behavioral of MAX is type STATE_TYPE is (S0, S1, S2, S3, S4); signal Current_State, Next_State: STATE_TYPE; signal x, y, mux : std_logic_vector (size-1 downto 0):= (others => '0'); signal z_sel, x_ld, y_ld, z_ld : std_logic := '0'; begin

Example – Cont. ----------------------------------------------- Reg_x: process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then x <= (others => '0'); else if (x_ld='1') then x <= x_i; end if; end process; Reg_y: process (CLK) y <= (others => '0'); if (y_ld='1') then y <= y_i; ----------------------------------------------- Reg_z_o:process (CLK) begin if (CLK'event and CLK='1') then if reset='1' then z_o <= (others => '0'); else if (z_ld='1') then z_o <= mux; end if; end process; Multiplexer: process (x, y, z_sel) if (z_sel='0') then mux <= x; elsif (z_sel='1') then mux <= y;

Example – Cont. ----------------------------------------------- SYNC_PROC: process (CLK, RESET) begin if (RESET='1') then Current_State <= S0; elsif (CLK'event and CLK = '1') then Current_State <= Next_State; end if; end process; ----------------------------------------------- COMB_PROC: process (Current_State, start, x, y, z_sel) begin case Current_State is -------------------------- when S0 => -- idle if (start='1') then Next_State <= S1; else Next_State <= S0; end if; when S1 => -- x = x_i & y = y_i x_ld <= '1'; y_ld <= '1'; z_ld <= '0' Next_State <= S2; when S2 => -- x ≥ y x_ld <= '0'; y_ld <= '0'; if (x >= y ) then Next_State <= S3; Next_State <= S4; when S3 => -- z = x z_sel <= '0'; z_ld<=’1’; when S4 => -- z = y z_sel <= '1'; end case; end process; ----------------------------------------------

Now, What’s Next ?!