Combinational Logic Design Chapter 0 – Week 2 Combinational Logic Design

What have been discussed Design hierarchy Top – down Bottom – up CAD (Comp. Aided Design) HDL (Hardware Description Language) Logic synthesis

Analysis Procedure Analysis To determine the function of a circuit Derive Boolean equation Derive truth table

Analyze this logic diagram

Boolean Equation T1 =BC T2 =AB T3 =A+T1=A+BC T4 =T2 + D = AB + D T5 =AB+D F1 = (A+BC) + (AB + D) F2 = T5 = AB + D

Analyze this Binary Adder C

Truth Table X Y Z C R1 R2 R3 S

Truth Table X Y Z 1 C R1 R2 R3 S 1

Logic Simulation A fast and accurate method of analyzing a combinational circuit Using simulator software Results : Waveforms A complete truth table Part of a truth table

Logic Simulation How is the circuit described in the software ? Schematics HDL

Schematic for Binary Adder in Xilinx

Waveforms for Binary Adder

Simulation in Max Plus II

Waveforms in MaxPlus II

Point to ponder…. Why do we compare the simulation results vs the theoretical results?

Design Procedure Given : Specifications of the problem Determine input & output Derive truth table Obtain Boolean equation (K-map) Draw schematics Verify design

Design of BCD to Excess – 3 Code Converter Specifications : Input in decimal numbers, 0 – 9, in binary form Output is excess – 3 code E.g Decimal = 5 (101) Excess – 3 code = 5 + 3 = 8 (1000)

BCD  Excess – 3 Step 1. Input : 0 to 9, 4 – bit binary code  A, B, C, D Output : 3 to 12, 4 – bit binary code  W, X, Y, Z

BCD  Excess – 3 Step 2 : Truth Table Dec 1 2 3 4 5 6 7 8 9 A B C D 1 1 2 3 4 5 6 7 8 9 A B C D 1 W X Y Z 1

BCD  Excess – 3 Step 3 : Boolean equation W = A + BC + BD X = BC + BD + BCD Y = CD + CD Z = D

BCD  Excess – 3 Step 4 : Schematic diagram

BCD  Excess – 3 Step 4 : Schematic diagram

BCD  Excess – 3 Step 5 : Verify that schematic diagram agrees with truth table

Design of BCD to 7 –segment decoder Specifications : Input in decimal numbers, 0 – 9, in binary form 7 Outputs – to display input number

7 – segment Display

BCD to 7 –segment decoder Step 1 :

BCD to 7 – segment decoder Step 2 : Truth Table A B C D 1 All other inputs a b c d e f g 1

Exercise A traffic light system has the following specifications for a part of its controller. There are 3 parallel lanes, each with its own red / green light. One of these lanes, the priority lane, is given priority for a green light over the other 2 lanes. On the other hand, an alternating scheme is used for the other 2 lanes, which are left and right lane. Design the circuit that determines which light is to be green at a particular time. The specifications for the controller are as follows :

Exercise Inputs : PS – Priority Lane Sensor ( car present = 1; car absent = 0 ) LS – Left Lane Sensor ( car present = 1; car absent = 0 ) RS – Right Lane Sensor ( car present = 1; car absent = 0 ) AS – Alternating Signal ( select left = 1; select right = 0 ) Outputs : PL – Priority Lane Light ( green = 1; red = 0 ) LL – Left Lane Light ( green = 1; red = 0 ) RL – Right Lane Light ( green = 1; red = 0 )

Exercise If there is a car in the priority lane, PL = 1. If there are no cars in the priority lane and the right lane, and there is a car in the left lane, LL = 1. If there are no cars in the priority lane and in the left lane, and there is a car in the right lane, RL = 1. If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 1, then LL = 1. If there is no car in the priority lane, there are cars in both the left and right lanes, and AS = 0, then RL = 1. If any PL, LL or RL is not specified to be 1 above, then it has value 0.

The End Let each day of your day be a masterpiece, cause today might be your last day to do it…