Overview of the project

Slides:



Advertisements
Similar presentations
Controller Tests Stephen Kaye Controller Test Motivation Testing the controller before the next generation helps to shake out any remaining.
Advertisements

Charge Pump PLL.
Lecture 17: Analog to Digital Converters Lecturers: Professor John Devlin Mr Robert Ross.
The MAD chip: 4 channel preamplifier + discriminator.
Digital to Analog and Analog to Digital Conversion
5/4/2006BAE Analog to Digital (A/D) Conversion An overview of A/D techniques.
Analogue to Digital Conversion
1 Analog-to-digital converter Prepared by: Selah al-Battah Mohammed Al-khabbaz Atiyah Alnakhli Ali Dumyati.
Test of LLRF at SPARC Marco Bellaveglia INFN – LNF Reporting for:
Front-end electronics for Time Projection Chamber I.Konorov Outlook:  TPC requirements  TPC readout options  Options for TPC FE chips  Prototype TPC.
Richard Kass IEEE NSS 11/14/ Richard Kass Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector K.E. Arms, K.K. Gan, M.
1/42 Changkun Park Title Dual mode RF CMOS Power Amplifier with transformer for polar transmitters March. 26, 2007 Changkun Park Wave Embedded Integrated.
Design Goal Design an Analog-to-Digital Conversion chip to meet demands of high quality voice applications such as: Digital Telephony, Digital Hearing.
Announcements Tuesday’s Lecture next week is cancelled –October 18 th Assignment 4 is active, due in my mailbox by 5pm Friday (October 14 th ) Mid-term.
19 March 2005 LCWS 05 M. Breidenbach 1 SiD Electronic Concepts SLAC –D. Freytag –G. Haller –J. Deng –mb Oregon –J. Brau –R. Frey –D. Strom BNL –V. Radeka.
LECC 2006 Ewald Effinger AB-BI-BL The LHC beam loss monitoring system’s data acquisition card Ewald Effinger AB-BI-BL.
The 555 as an Astable Multivibrator. Inside look at a 555 Integrated Circuit Timer.
Designs and Implementation Ring Detector circuit Design: Ring Detector circuit Design:
Phase Locked Loops Continued
Calorimeter upgrade meeting – CERN – October 5 th 2010 Analog FE ASIC: first prototype Upgrade of the front end electronics of the LHCb calorimeter E.
Department of Electrical & Computer Engineering 1 ES585a - Computer Based Power System Protection Course by Dr.T.S.Sidhu - Fall 2005 Class discussion presentation.
A radiation-tolerant LDO voltage regulator for HEP applications F.Faccio, P.Moreira, A.Marchioro, S.Velitchko CERN.
A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group.
L. Gallin-Martel, D. Dzahini, F. Rarbi, O. Rossetto
Engineering Lecture1: Logic Circuits & Concepts about basic Electrical Engineering Devices by Christin Sander.
Adopting Multi-Valued Logic for Reduced Pin-Count Testing Baohu Li, Bei Zhang and Vishwani Agrawal Auburn University, ECE Dept., Auburn, AL 36849, USA.
Pierpaolo Valerio.  CLICpix is a hybrid pixel detector to be used as the CLIC vertex detector  Main features: ◦ small pixel pitch (25 μm), ◦ Simultaneous.
Announcements mid-term Thursday (Oct 27 th ) Project ideas to me by Nov 1 st latest Assignment 4 due tomorrow (or now) Assignment 5 posted, due Friday.
Filip Tavernier Karolina Poltorak Sandro Bonacini Paulo Moreira
PHY 202 (Blum)1 Analog-to-Digital Converter and Multi-vibrators.
Self triggered readout of GEM in CBM J. Saini VECC, Kolkata.
8/9/2000T.Matsumoto RICH Front End RICH FEE Overview PMT to FEE signal connection Trigger Tile Summation of Current RICH LVL-1 Trigger Module1,2 What is.
25th June, 2003CMS Ecal MGPA first results1 MGPA first results testing begun 29 th May on bare die (packaging still underway) two chips looked at so far.
The AFTER electronics from a user’s point of view D. Attié, P. Colas Mamma meeting,CERN Feb T2K electronics.
Acquisition Crate Design BI Technical Board 26 August 2011 Beam Loss Monitoring Section William Vigano’ 26 August
BLM AUDIT 2010Ewald Effinger BE-BI-BL BLM tunnel installation and data acquisition card (BLECF) Ewald Effinger AB-BI-BL.
L.Royer– Calice LLR – Feb Laurent Royer, J. Bonnard, S. Manen, P. Gay LPC Clermont-Ferrand R&D pole MicRhAu dedicated to High.
ASIC Activities for the PANDA GSI Peter Wieczorek.
BeamCal Electronics Status FCAL Collaboration Meeting LAL-Orsay, October 5 th, 2007 Gunther Haller, Dietrich Freytag, Martin Breidenbach and Angel Abusleme.
LC Power Distribution & Pulsing Workshop, May 2011 Super-ALTRO Demonstrator Test Results LC Power Distribution & Pulsing Workshop, May nd November.
A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade Tiankuan Liu On behalf of the ATLAS Liquid Argon Calorimeter Group Department of.
Fermilab Silicon Strip Readout Chip for BTEV
Low Power, High-Throughput AD Converters
S. Bota – Calorimeter Electronics overview - July 2002 Status of SPD electronics Very Front End Review of ASIC runs What’s new: RUN 4 and 5 Next Actions.
Standard electronics for CLIC module. Sébastien Vilalte CTC
NOISE MEASUREMENTS ON CLICPIX AND FUTURE DEVELOPMENTS Pierpaolo Valerio.
Sequential Logic An Overview
2007 IEEE Nuclear Science Symposium (NSS)
Jinfan Chang Experimental Physics Center , IHEP Feb 18 , 2011
CTA-LST meeting February 2015
96-channel, 10-bit, 20 MSPS ADC board with Gb Ethernet optical output
DCH FEE 28 chs DCH prototype FEE &
Hugo França-Santos - CERN
Meeting at CERN March 2011.
LHC BLM system: system overview
ALCT Production, Cable Tests, and TMB Status
A Low Power Readout ASIC for Time Projection Chambers in 65nm CMOS
EUDET – LPC- Clermont VFE Electronics
LHCb calorimeter main features
Created by Luis Chioye Presented by Cynthia Sosa
Driving, conditioning and signal acquisition
SiD Electronic Concepts
Chis status report.
Stefan Ritt Paul Scherrer Institute, Switzerland
Analog-to-digital converter
Mark Bristow CENBD 452 Fall 2002
Presented by T. Suomijärvi
A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC
Lecture 22: PLLs and DLLs.
A 12 bit 50 MS/s Dual Channel Time Domain Two Step ADC
Presentation transcript:

Overview of the project BLM ASIC V3 Overview of the project 29/06/2017 F. Zappon

Outline BLM ASIC: motivation Development history Architecture 1: Adaptive Current-to-Frequency Converter Architecture 2: DeltaSigma Converter Planning and future developments 29/06/2017 F. Zappon

BLM ASIC: motivation Arc sections Collimators and triplets Idea behind the project: Remove the cables and the CFC card Place a readout chip next to the ionization chambers Send digital data through optical link to the surface BLM ASIC development 29/06/2017 F. Zappon

BLM ASIC: new setup under study Some ASIC specifications: Dynamic range: 1 pA – 1 mA Dual polarity input Radiation hard: Total Ionizing Dose 10 kGy in 20 years  no FPGA on board 29/06/2017 F. Zappon

Development history V2.1 back at CERN Submission V2 Test of V1 Test of V2.1 2009 2010 2011 2012 2013 2014 2015 2016 2017 Design V1 Submission of V1 Design V2 Test V2 Submission V2.1 Development of V3 begins Notice: Technology change in V3: 250 nm  130 nm Project is “restarting” Possibility to explore other ideas for the architecture Fall-back to V2 architecture if problems arise 29/06/2017 F. Zappon

Architecture 1: Current-to-Frequency Converter Basic concept Cycle of operation (ideal) based on the charge-balance principle: Input current is integrated When the output voltage of the integrator reaches a predetermined threshold, the (clocked) comparator “fires” The comparator output pulse activates a current source The current source is used to discharge the integrator to the initial value The frequency of the output pulses is related to the input current: f=Iin/Qref 29/06/2017 F. Zappon

Adaptive CFC Used in V1.0 and V2.X Dynamic range is divided in 4 sub-ranges For each range the logic selects the appropriate values for Feedback capacitor Discharge current Fully differential architecture guarantees good noise rejection Reinjection of charge when disconnecting a capacitor Requires 2 additional bits to be sent to have information on the range Digital logic decides when to switch based on the input current 29/06/2017 F. Zappon

Waveform example - CFC Output bitstream 29/06/2017 F. Zappon

Test results Ref: G. Venturini et al, A 120 dB dynamic-range radiation-tolerant charge-to-digital converter for radiation monitoring, Microelectronics Journal, vol. 44, Issue 12, 2013 https://doi.org/10.1016/j.mejo.2013.08.020 29/06/2017 F. Zappon

Architecture 2: Delta-Sigma Converter Input current is integrated Value of the integrator is compared to threshold (out is 0/1) at each rising edge of the clock According to out, the 1-bit DAC subtract a certain amount of charge from the input Over time, the “average” of the output follows the input The output bitstream is “decimated” by a digital filter, implemented in the FPGA to get the value of the input Very important concept for DS: oversampling! 29/06/2017 F. Zappon

Implementation: Multi Bit Delta-Sigma Converter Image courtesy of F. Martina 29/06/2017 F. Zappon

Waveform example – 1st order DeltaSigma Output bitstream Input signal 29/06/2017 F. Zappon

Simulation results – Numerical simulations Image courtesy of F. Martina 29/06/2017 F. Zappon

Architectures comparison Bit pattern: similar – but DeltaSigma has higher frequency In both cases (CFC with multiple threshold or Multi-bit DeltaSigma) we need to send out of chip additional bits to have the information about the charge subtracted CFC requires a Digital State Machine, while DeltaSigma is “self-adjusting” Both architectures require radiation hard techniques, but DeltaSigma is less prone to digital problems (SEU) There is a bit pattern for DeltaSigma with zero input current (no need to inject a current to trigger the frontend?) Charge subtraction in the CFC happens only when the signal is over threshold at the rising edge of the clock while it is “continuous” in the DS. 29/06/2017 F. Zappon

Planning A bit optimistic, but currently on track! Target: submit chip to foundry in 1 year, i.e.: April 2018 April May June July Aug. Sept. Oct. Nov. Dec. Jan. Feb. march System level studies Transistor level design and simulations Layout and simulations Signoff A bit optimistic, but currently on track! Bonus: implement a discrete-component version of the DeltaSigma architecture. Cons: might create a delay Pro: will give insights on the “real world” problems that the final circuit might encounter and we might be able to plan in advance for those issues (plus: proof of principle, which is always good). 29/06/2017 F. Zappon

29/06/2017 F. Zappon

CFC: design values Range Min. I (A) Max I (A) Feed. C (pC) Ref. charge Thr. Volt. 1*10-9 256*10-9 0.32 0.04 0.125 1 160*10-9 4.1*10-6 2.56 0.64 0.25 2 2.56*10-6 65.5*10-6 20.5 10.24 0.5 3 41*10-6 1*10-3 164 163.84 29/06/2017 F. Zappon