Discussions on hw5 Objectives: Implement multitasking of 3 processes using a preemptive scheduler Process 1 Process 2 Process 3 Process 0

Preemptive Scheduler Program Flow startup0.s: Same as $pclibsrc/startup0.s - init stack Start from Tutor startup1.c: init kernel Part of tunix.c: modified from hw3 -call ioinit, set_trap_gate(0x80, &syscall): -init PEntry[] for Proc 0,1,2,3 -call tickinit to set up timer0 -call schedule() to start Proc 0 Init memory Init kernel sched.c: modified from hw3; see 2.4 in hw5.doc -schedule() ; sleep(); wakeup() -call asmswtch which calls _ustart1, _ustart2, or _ustart3 Scheduler Start-up crt01.s, crt02.s,crt03.s: same as hw3 -entry points:_ustart1, _ustart2, _ustart3 -call _main1, _main2, or _main3 -call _exit Start-up Start-up User program User program uprog123.c: modified from hw3’s uprog1, uprog2,uprog3.c -entry points: main1, main2, main3 -call write User program lib calls to do write, exit ulib.s: same as hw3; -call _write, _exit

Kernel Program Flows-syscall sysentry.s: same as hw3 -push eax,ebx,ecx,edx on stack -call system call dispatcher: _syscallc -pop stack and iret Trap handler wrapper System call dispatcher Part of tunix.c: modified from hw3 -entry point _syscallc -depend on syscall #, call the handler routine -need to modify sysexit to add protection for Zombie count System call trap handler routine tty.c: same as hw3 -wakeup at irqinthandc for tx interrupt -sleep at ttywrite when queue is full

Programmable Interval Timer This is an overview from CS341 lectures Detailed Intel 8254 spec sheet in www.cs.umb.edu/~cheungr/cs341/I8254PIT.pdf 8254 VLSI chip with three 16 bit counters Each counter: Is decremented based on its own input clock Is only decremented while its gate is active Generates its own output clock frequency = input clock / count length Generates an interrupt when count value reaches zero Automatically reloads initial value when it reaches zero

PIT Device (Timer 0) Simplest device: interrupts every time it counts down to zero Can’t disable interrupts in this device! Can mask them off in the PIC We can control how often it interrupts Timer doesn’t keep track of interrupts in progress - just keeps sending them in We don’t need to interact with it in the ISR (but we do need to send an EOI to the PIC)

Use of PIT in hw5 $pcex/timetest.c gives you a start for the required C code. You add to it. You should study the C code to understand how it works: Find where code disables and enables interrupts Find the PIT initialization code Find the PIT ISR code and see what it does The code generates a timer interrupt every 55 ms and you need to change it to every 10 ms, like Linux. It will print out a “*” for every tick. Take out the print out when you do the final testing on hw5

PIT Counter in timetest.c We set PIT Timer 0’s counter=0 to generate an interrupt every 55 millisecs 1.1931817 MHz /65536 =18.2.Hz For a 20msec tick, we compute the counter value: 1.1931817 x 106 x 20 x 10-3 = 23864 =0x5d38 ISR performs functions needed (e.g. increment icount in timertest.c)

Timer Interrupt Software Initialization Disallow interrupts in CPU (cli) To allow timer interrupts, unmask IRQ0 in the PIC by ensuring bit 0 is 0 in the Interrupt Mask Register (port 0x21) Set up interrupt gate descriptor in IDT, using irq0inthand Set up timer downcount to determine tick interval Allow interrupts (sti) Shutdown Disallow interrupts (cli) Disallow timer interrupts by masking IRQ0 in the PIC by making bit 0 be 1 in the Interrupt Mask Register (port 0x21)

Timer Interrupts: Interrupt Handler (Two Parts) irq0inthand – the outer assembly language interrupt handler Save registers Calls C function irq0inthandc Restore registers iret irq0inthandc - the C interrupt handler Issues EOI Print out “*” and increase icount, or whatever is wanted

PIT Characteristics PIT chip has four I/O ports assigned to it: A1 A0 Timer 0 assigned port 40 = 0100 0000 Timer 1 assigned port 41 = 0100 0001 Timer 2 assigned port 42 = 0100 0010 Control assigned port 43 = 0100 0011 Chip selected by “chip select” and A1-A0 Other signals include read, write, and data

Control Word Format Actually only a byte: SC1-SC0 select which counter to write/read RW1-RW0 to latch value or select which byte of count value M2-M0 determines which operating mode BCD specifies whether binary or BCD count Command formats found in datasheet SC1 SC0 RW1 RW0 M2 M1 M0 BCD

Using the PIT in C Refer to timer.h #define TIMER0_COUNT_PORT 0X40 #define TIMER_CNTRL_PORT 0X43 /* bits 6-7: */ #define TIMER0 (O<<6) #define TIMER1 (1<<6) /* Bits 4-5 */ #define TIMER_LATCH (0<<4) #define TIMER_SET_ALL (3<<4) /* Bits 1-3 */ #define TIMER_MODE_RATEGEN (2<<1) /* Bit 0 */ #define TIMER_BINARY_COUNTER 0 R/W LS byte and then MS byte

Programming the PIT Bits to initialize Output to the timer I/O port TIMER0 | TIMER_SET_ALL | TIMER_MODE_RATEGEN |TIMER_BINARY_COUNTER Output to the timer I/O port outpt(TIMER_CNTRL_PORT, …); Then load the downcount outpt(TIMER0_COUNT_PORT, count & 0xFF); // LSByte outpt(TIMER0_COUNT_PORT, count >> 8); // MSByte

What Are the PIT Modes? Mode 0: Count value loaded and countdown occurs on every clock signal; Out from counter remains low until count reaches 0 when it goes high Mode 2: Counts down from loaded value; when count has decremented to 1, OUT goes low for one clock pulse and then goes high again; count is reloaded and process repeats Count = 1 Count = 0

What Are the PIT Modes? (Cont’d) Mode 3: Functions as a divide by n square wave generator, where n is the count value; OUT starts high and alternates between low and high. In hw5, we use Mode 2

More Discussions on hw5 Timer interrupts Kernel uses ticks for: called ticks. ISR called tick handler Kernel uses ticks for: time keeping, incrementing the global system time variable counting down the quantum and causing preemption when it reaches zero handling periodic housekeeping actions other time-delayed actions such as network timeouts

How to Handle the Quantum Add a new member p_quantum to PEntry data structure To set a quantum of QUANTUM ms, initialize p_quantum =QUANTUM Example code in timer ISR: if(--curproc->p_quantum = = 0) { /* preempting, start over with full quantum */ curproc->p_quantum = QUANTUM; schedule(); /* find another process to run */ } Code runs with IF=0, so do not use sti Important to realize that the tick handler is counting down the current process curproc

Preemption in Kernel Code Don’t know a tick happened in user or kernel code. Preemption happens in both. Both Solaris and Win2K allows kernel preemption. Linux v2.6 allows unlimited preemption Preemption occurs in kernel code where IF=1 Race conditions can occur with kernel global variables (e.g. in hw3 : number_of_zombie++;) Lost Update Problem: proc 1 exec the first instruction and then get preempted. Proc 2 exec both instructions. Proc 1 resumes and updates the old value Assembled into: 1. Read value 2. Increment and store

More on Lost Update Problem Solution: Use kernel mutex For hw5, make IF = 0 for this code This only happens to global variables For local variables, this is not an issue: Updates occur only on the process’s private stack Updates on one process do not affect another

Preemptive Scheduler in CPU-bound tasks With hw3’s non-preemptive scheduler, output stops during the running of the CPU-bound tasks, . Example in main1 of uprog1.c: Preemptive scheduler in hw5 will change this I/O bound I/O bound CPU bound No output …a a a z z z-------------------AAA...

Process Switching In hw3’s scheduler, the decision for running the next process is round robin is process 1 runnable? Run it if it is. Is process 2 runnable? Run it if it is. … In hw5’s scheduler, we want the decision to be: if process 1 is running now, run process 2 if it is runnable if process 2 is running now, run process 3 if it is runnable ...